0e133a1337
There's different mathematical definitions (truncated, floored, rounded, etc.) and different languages have chosen different definitions [0][1]. E.g., languages/libraries that follow Knuth use a different mathematical definition than C uses. This patch specifies which definition BPF uses, as verified by Eduard [2] and others. [0] https://en.wikipedia.org/wiki/Modulo#Variants_of_the_definition [1] https://torstencurdt.com/tech/posts/modulo-of-negative-numbers/ [2] https://lore.kernel.org/bpf/57e6fefadaf3b2995bb259fa8e711c7220ce5290.camel@gmail.com/ Signed-off-by: Dave Thaler <dthaler@microsoft.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: David Vernet <void@manifault.com> Acked-by: Eduard Zingerman <eddyz87@gmail.com> Link: https://lore.kernel.org/bpf/20231017203020.1500-1-dthaler1968@googlemail.com
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.. contents::
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.. sectnum::
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=======================================
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BPF Instruction Set Specification, v1.0
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=======================================
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This document specifies version 1.0 of the BPF instruction set.
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Documentation conventions
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=========================
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For brevity and consistency, this document refers to families
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of types using a shorthand syntax and refers to several expository,
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mnemonic functions when describing the semantics of instructions.
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The range of valid values for those types and the semantics of those
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functions are defined in the following subsections.
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Types
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-----
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This document refers to integer types with the notation `SN` to specify
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a type's signedness (`S`) and bit width (`N`), respectively.
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.. table:: Meaning of signedness notation.
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==== =========
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`S` Meaning
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==== =========
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`u` unsigned
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`s` signed
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==== =========
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.. table:: Meaning of bit-width notation.
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===== =========
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`N` Bit width
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===== =========
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`8` 8 bits
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`16` 16 bits
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`32` 32 bits
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`64` 64 bits
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`128` 128 bits
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===== =========
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For example, `u32` is a type whose valid values are all the 32-bit unsigned
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numbers and `s16` is a types whose valid values are all the 16-bit signed
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numbers.
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Functions
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---------
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* `htobe16`: Takes an unsigned 16-bit number in host-endian format and
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returns the equivalent number as an unsigned 16-bit number in big-endian
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format.
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* `htobe32`: Takes an unsigned 32-bit number in host-endian format and
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returns the equivalent number as an unsigned 32-bit number in big-endian
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format.
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* `htobe64`: Takes an unsigned 64-bit number in host-endian format and
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returns the equivalent number as an unsigned 64-bit number in big-endian
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format.
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* `htole16`: Takes an unsigned 16-bit number in host-endian format and
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returns the equivalent number as an unsigned 16-bit number in little-endian
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format.
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* `htole32`: Takes an unsigned 32-bit number in host-endian format and
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returns the equivalent number as an unsigned 32-bit number in little-endian
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format.
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* `htole64`: Takes an unsigned 64-bit number in host-endian format and
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returns the equivalent number as an unsigned 64-bit number in little-endian
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format.
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* `bswap16`: Takes an unsigned 16-bit number in either big- or little-endian
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format and returns the equivalent number with the same bit width but
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opposite endianness.
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* `bswap32`: Takes an unsigned 32-bit number in either big- or little-endian
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format and returns the equivalent number with the same bit width but
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opposite endianness.
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* `bswap64`: Takes an unsigned 64-bit number in either big- or little-endian
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format and returns the equivalent number with the same bit width but
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opposite endianness.
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Definitions
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-----------
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.. glossary::
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Sign Extend
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To `sign extend an` ``X`` `-bit number, A, to a` ``Y`` `-bit number, B ,` means to
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#. Copy all ``X`` bits from `A` to the lower ``X`` bits of `B`.
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#. Set the value of the remaining ``Y`` - ``X`` bits of `B` to the value of
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the most-significant bit of `A`.
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.. admonition:: Example
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Sign extend an 8-bit number ``A`` to a 16-bit number ``B`` on a big-endian platform:
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::
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A: 10000110
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B: 11111111 10000110
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Instruction encoding
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====================
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BPF has two instruction encodings:
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* the basic instruction encoding, which uses 64 bits to encode an instruction
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* the wide instruction encoding, which appends a second 64-bit immediate (i.e.,
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constant) value after the basic instruction for a total of 128 bits.
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The fields conforming an encoded basic instruction are stored in the
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following order::
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opcode:8 src_reg:4 dst_reg:4 offset:16 imm:32 // In little-endian BPF.
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opcode:8 dst_reg:4 src_reg:4 offset:16 imm:32 // In big-endian BPF.
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**imm**
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signed integer immediate value
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**offset**
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signed integer offset used with pointer arithmetic
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**src_reg**
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the source register number (0-10), except where otherwise specified
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(`64-bit immediate instructions`_ reuse this field for other purposes)
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**dst_reg**
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destination register number (0-10)
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**opcode**
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operation to perform
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Note that the contents of multi-byte fields ('imm' and 'offset') are
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stored using big-endian byte ordering in big-endian BPF and
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little-endian byte ordering in little-endian BPF.
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For example::
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opcode offset imm assembly
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src_reg dst_reg
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07 0 1 00 00 44 33 22 11 r1 += 0x11223344 // little
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dst_reg src_reg
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07 1 0 00 00 11 22 33 44 r1 += 0x11223344 // big
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Note that most instructions do not use all of the fields.
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Unused fields shall be cleared to zero.
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As discussed below in `64-bit immediate instructions`_, a 64-bit immediate
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instruction uses a 64-bit immediate value that is constructed as follows.
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The 64 bits following the basic instruction contain a pseudo instruction
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using the same format but with opcode, dst_reg, src_reg, and offset all set to zero,
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and imm containing the high 32 bits of the immediate value.
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This is depicted in the following figure::
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basic_instruction
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.-----------------------------.
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code:8 regs:8 offset:16 imm:32 unused:32 imm:32
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'--------------'
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pseudo instruction
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Thus the 64-bit immediate value is constructed as follows:
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imm64 = (next_imm << 32) | imm
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where 'next_imm' refers to the imm value of the pseudo instruction
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following the basic instruction. The unused bytes in the pseudo
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instruction are reserved and shall be cleared to zero.
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Instruction classes
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-------------------
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The three LSB bits of the 'opcode' field store the instruction class:
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========= ===== =============================== ===================================
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class value description reference
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========= ===== =============================== ===================================
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BPF_LD 0x00 non-standard load operations `Load and store instructions`_
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BPF_LDX 0x01 load into register operations `Load and store instructions`_
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BPF_ST 0x02 store from immediate operations `Load and store instructions`_
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BPF_STX 0x03 store from register operations `Load and store instructions`_
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BPF_ALU 0x04 32-bit arithmetic operations `Arithmetic and jump instructions`_
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BPF_JMP 0x05 64-bit jump operations `Arithmetic and jump instructions`_
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BPF_JMP32 0x06 32-bit jump operations `Arithmetic and jump instructions`_
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BPF_ALU64 0x07 64-bit arithmetic operations `Arithmetic and jump instructions`_
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========= ===== =============================== ===================================
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Arithmetic and jump instructions
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================================
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For arithmetic and jump instructions (``BPF_ALU``, ``BPF_ALU64``, ``BPF_JMP`` and
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``BPF_JMP32``), the 8-bit 'opcode' field is divided into three parts:
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============== ====== =================
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4 bits (MSB) 1 bit 3 bits (LSB)
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============== ====== =================
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code source instruction class
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============== ====== =================
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**code**
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the operation code, whose meaning varies by instruction class
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**source**
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the source operand location, which unless otherwise specified is one of:
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====== ===== ==============================================
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source value description
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====== ===== ==============================================
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BPF_K 0x00 use 32-bit 'imm' value as source operand
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BPF_X 0x08 use 'src_reg' register value as source operand
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====== ===== ==============================================
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**instruction class**
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the instruction class (see `Instruction classes`_)
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Arithmetic instructions
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-----------------------
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``BPF_ALU`` uses 32-bit wide operands while ``BPF_ALU64`` uses 64-bit wide operands for
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otherwise identical operations.
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The 'code' field encodes the operation as below, where 'src' and 'dst' refer
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to the values of the source and destination registers, respectively.
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========= ===== ======= ==========================================================
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code value offset description
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========= ===== ======= ==========================================================
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BPF_ADD 0x00 0 dst += src
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BPF_SUB 0x10 0 dst -= src
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BPF_MUL 0x20 0 dst \*= src
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BPF_DIV 0x30 0 dst = (src != 0) ? (dst / src) : 0
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BPF_SDIV 0x30 1 dst = (src != 0) ? (dst s/ src) : 0
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BPF_OR 0x40 0 dst \|= src
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BPF_AND 0x50 0 dst &= src
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BPF_LSH 0x60 0 dst <<= (src & mask)
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BPF_RSH 0x70 0 dst >>= (src & mask)
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BPF_NEG 0x80 0 dst = -dst
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BPF_MOD 0x90 0 dst = (src != 0) ? (dst % src) : dst
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BPF_SMOD 0x90 1 dst = (src != 0) ? (dst s% src) : dst
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BPF_XOR 0xa0 0 dst ^= src
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BPF_MOV 0xb0 0 dst = src
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BPF_MOVSX 0xb0 8/16/32 dst = (s8,s16,s32)src
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BPF_ARSH 0xc0 0 :term:`sign extending<Sign Extend>` dst >>= (src & mask)
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BPF_END 0xd0 0 byte swap operations (see `Byte swap instructions`_ below)
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========= ===== ======= ==========================================================
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Underflow and overflow are allowed during arithmetic operations, meaning
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the 64-bit or 32-bit value will wrap. If BPF program execution would
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result in division by zero, the destination register is instead set to zero.
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If execution would result in modulo by zero, for ``BPF_ALU64`` the value of
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the destination register is unchanged whereas for ``BPF_ALU`` the upper
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32 bits of the destination register are zeroed.
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``BPF_ADD | BPF_X | BPF_ALU`` means::
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dst = (u32) ((u32) dst + (u32) src)
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where '(u32)' indicates that the upper 32 bits are zeroed.
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``BPF_ADD | BPF_X | BPF_ALU64`` means::
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dst = dst + src
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``BPF_XOR | BPF_K | BPF_ALU`` means::
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dst = (u32) dst ^ (u32) imm32
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``BPF_XOR | BPF_K | BPF_ALU64`` means::
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dst = dst ^ imm32
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Note that most instructions have instruction offset of 0. Only three instructions
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(``BPF_SDIV``, ``BPF_SMOD``, ``BPF_MOVSX``) have a non-zero offset.
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The division and modulo operations support both unsigned and signed flavors.
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For unsigned operations (``BPF_DIV`` and ``BPF_MOD``), for ``BPF_ALU``,
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'imm' is interpreted as a 32-bit unsigned value. For ``BPF_ALU64``,
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'imm' is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
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interpreted as a 64-bit unsigned value.
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For signed operations (``BPF_SDIV`` and ``BPF_SMOD``), for ``BPF_ALU``,
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'imm' is interpreted as a 32-bit signed value. For ``BPF_ALU64``, 'imm'
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is first :term:`sign extended<Sign Extend>` from 32 to 64 bits, and then
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interpreted as a 64-bit signed value.
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Note that there are varying definitions of the signed modulo operation
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when the dividend or divisor are negative, where implementations often
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vary by language such that Python, Ruby, etc. differ from C, Go, Java,
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etc. This specification requires that signed modulo use truncated division
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(where -13 % 3 == -1) as implemented in C, Go, etc.:
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a % n = a - n * trunc(a / n)
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The ``BPF_MOVSX`` instruction does a move operation with sign extension.
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``BPF_ALU | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit and 16-bit operands into 32
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bit operands, and zeroes the remaining upper 32 bits.
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``BPF_ALU64 | BPF_MOVSX`` :term:`sign extends<Sign Extend>` 8-bit, 16-bit, and 32-bit
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operands into 64 bit operands.
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Shift operations use a mask of 0x3F (63) for 64-bit operations and 0x1F (31)
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for 32-bit operations.
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Byte swap instructions
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----------------------
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The byte swap instructions use instruction classes of ``BPF_ALU`` and ``BPF_ALU64``
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and a 4-bit 'code' field of ``BPF_END``.
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The byte swap instructions operate on the destination register
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only and do not use a separate source register or immediate value.
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For ``BPF_ALU``, the 1-bit source operand field in the opcode is used to
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select what byte order the operation converts from or to. For
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``BPF_ALU64``, the 1-bit source operand field in the opcode is reserved
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and must be set to 0.
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========= ========= ===== =================================================
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class source value description
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========= ========= ===== =================================================
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BPF_ALU BPF_TO_LE 0x00 convert between host byte order and little endian
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BPF_ALU BPF_TO_BE 0x08 convert between host byte order and big endian
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BPF_ALU64 Reserved 0x00 do byte swap unconditionally
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========= ========= ===== =================================================
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The 'imm' field encodes the width of the swap operations. The following widths
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are supported: 16, 32 and 64.
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Examples:
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``BPF_ALU | BPF_TO_LE | BPF_END`` with imm = 16/32/64 means::
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dst = htole16(dst)
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dst = htole32(dst)
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dst = htole64(dst)
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``BPF_ALU | BPF_TO_BE | BPF_END`` with imm = 16/32/64 means::
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dst = htobe16(dst)
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dst = htobe32(dst)
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dst = htobe64(dst)
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``BPF_ALU64 | BPF_TO_LE | BPF_END`` with imm = 16/32/64 means::
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dst = bswap16(dst)
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dst = bswap32(dst)
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dst = bswap64(dst)
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Jump instructions
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-----------------
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``BPF_JMP32`` uses 32-bit wide operands while ``BPF_JMP`` uses 64-bit wide operands for
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otherwise identical operations.
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The 'code' field encodes the operation as below:
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======== ===== === =========================================== =========================================
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code value src description notes
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======== ===== === =========================================== =========================================
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BPF_JA 0x0 0x0 PC += offset BPF_JMP class
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BPF_JA 0x0 0x0 PC += imm BPF_JMP32 class
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BPF_JEQ 0x1 any PC += offset if dst == src
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BPF_JGT 0x2 any PC += offset if dst > src unsigned
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BPF_JGE 0x3 any PC += offset if dst >= src unsigned
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BPF_JSET 0x4 any PC += offset if dst & src
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BPF_JNE 0x5 any PC += offset if dst != src
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BPF_JSGT 0x6 any PC += offset if dst > src signed
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BPF_JSGE 0x7 any PC += offset if dst >= src signed
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BPF_CALL 0x8 0x0 call helper function by address see `Helper functions`_
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BPF_CALL 0x8 0x1 call PC += imm see `Program-local functions`_
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BPF_CALL 0x8 0x2 call helper function by BTF ID see `Helper functions`_
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BPF_EXIT 0x9 0x0 return BPF_JMP only
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BPF_JLT 0xa any PC += offset if dst < src unsigned
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BPF_JLE 0xb any PC += offset if dst <= src unsigned
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BPF_JSLT 0xc any PC += offset if dst < src signed
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BPF_JSLE 0xd any PC += offset if dst <= src signed
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======== ===== === =========================================== =========================================
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The BPF program needs to store the return value into register R0 before doing a
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``BPF_EXIT``.
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Example:
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``BPF_JSGE | BPF_X | BPF_JMP32`` (0x7e) means::
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if (s32)dst s>= (s32)src goto +offset
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where 's>=' indicates a signed '>=' comparison.
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``BPF_JA | BPF_K | BPF_JMP32`` (0x06) means::
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gotol +imm
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where 'imm' means the branch offset comes from insn 'imm' field.
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Note that there are two flavors of ``BPF_JA`` instructions. The
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``BPF_JMP`` class permits a 16-bit jump offset specified by the 'offset'
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field, whereas the ``BPF_JMP32`` class permits a 32-bit jump offset
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specified by the 'imm' field. A > 16-bit conditional jump may be
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converted to a < 16-bit conditional jump plus a 32-bit unconditional
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jump.
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Helper functions
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~~~~~~~~~~~~~~~~
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Helper functions are a concept whereby BPF programs can call into a
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set of function calls exposed by the underlying platform.
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Historically, each helper function was identified by an address
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encoded in the imm field. The available helper functions may differ
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for each program type, but address values are unique across all program types.
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Platforms that support the BPF Type Format (BTF) support identifying
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a helper function by a BTF ID encoded in the imm field, where the BTF ID
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identifies the helper name and type.
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Program-local functions
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~~~~~~~~~~~~~~~~~~~~~~~
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Program-local functions are functions exposed by the same BPF program as the
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caller, and are referenced by offset from the call instruction, similar to
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``BPF_JA``. The offset is encoded in the imm field of the call instruction.
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A ``BPF_EXIT`` within the program-local function will return to the caller.
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Load and store instructions
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===========================
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For load and store instructions (``BPF_LD``, ``BPF_LDX``, ``BPF_ST``, and ``BPF_STX``), the
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8-bit 'opcode' field is divided as:
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============ ====== =================
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3 bits (MSB) 2 bits 3 bits (LSB)
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============ ====== =================
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mode size instruction class
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============ ====== =================
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The mode modifier is one of:
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============= ===== ==================================== =============
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mode modifier value description reference
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============= ===== ==================================== =============
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BPF_IMM 0x00 64-bit immediate instructions `64-bit immediate instructions`_
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BPF_ABS 0x20 legacy BPF packet access (absolute) `Legacy BPF Packet access instructions`_
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BPF_IND 0x40 legacy BPF packet access (indirect) `Legacy BPF Packet access instructions`_
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BPF_MEM 0x60 regular load and store operations `Regular load and store operations`_
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BPF_MEMSX 0x80 sign-extension load operations `Sign-extension load operations`_
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BPF_ATOMIC 0xc0 atomic operations `Atomic operations`_
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============= ===== ==================================== =============
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The size modifier is one of:
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============= ===== =====================
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size modifier value description
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============= ===== =====================
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BPF_W 0x00 word (4 bytes)
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BPF_H 0x08 half word (2 bytes)
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BPF_B 0x10 byte
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BPF_DW 0x18 double word (8 bytes)
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============= ===== =====================
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Regular load and store operations
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---------------------------------
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The ``BPF_MEM`` mode modifier is used to encode regular load and store
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instructions that transfer data between a register and memory.
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``BPF_MEM | <size> | BPF_STX`` means::
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*(size *) (dst + offset) = src
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``BPF_MEM | <size> | BPF_ST`` means::
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*(size *) (dst + offset) = imm32
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``BPF_MEM | <size> | BPF_LDX`` means::
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dst = *(unsigned size *) (src + offset)
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Where size is one of: ``BPF_B``, ``BPF_H``, ``BPF_W``, or ``BPF_DW`` and
|
|
'unsigned size' is one of u8, u16, u32 or u64.
|
|
|
|
Sign-extension load operations
|
|
------------------------------
|
|
|
|
The ``BPF_MEMSX`` mode modifier is used to encode :term:`sign-extension<Sign Extend>` load
|
|
instructions that transfer data between a register and memory.
|
|
|
|
``BPF_MEMSX | <size> | BPF_LDX`` means::
|
|
|
|
dst = *(signed size *) (src + offset)
|
|
|
|
Where size is one of: ``BPF_B``, ``BPF_H`` or ``BPF_W``, and
|
|
'signed size' is one of s8, s16 or s32.
|
|
|
|
Atomic operations
|
|
-----------------
|
|
|
|
Atomic operations are operations that operate on memory and can not be
|
|
interrupted or corrupted by other access to the same memory region
|
|
by other BPF programs or means outside of this specification.
|
|
|
|
All atomic operations supported by BPF are encoded as store operations
|
|
that use the ``BPF_ATOMIC`` mode modifier as follows:
|
|
|
|
* ``BPF_ATOMIC | BPF_W | BPF_STX`` for 32-bit operations
|
|
* ``BPF_ATOMIC | BPF_DW | BPF_STX`` for 64-bit operations
|
|
* 8-bit and 16-bit wide atomic operations are not supported.
|
|
|
|
The 'imm' field is used to encode the actual atomic operation.
|
|
Simple atomic operation use a subset of the values defined to encode
|
|
arithmetic operations in the 'imm' field to encode the atomic operation:
|
|
|
|
======== ===== ===========
|
|
imm value description
|
|
======== ===== ===========
|
|
BPF_ADD 0x00 atomic add
|
|
BPF_OR 0x40 atomic or
|
|
BPF_AND 0x50 atomic and
|
|
BPF_XOR 0xa0 atomic xor
|
|
======== ===== ===========
|
|
|
|
|
|
``BPF_ATOMIC | BPF_W | BPF_STX`` with 'imm' = BPF_ADD means::
|
|
|
|
*(u32 *)(dst + offset) += src
|
|
|
|
``BPF_ATOMIC | BPF_DW | BPF_STX`` with 'imm' = BPF ADD means::
|
|
|
|
*(u64 *)(dst + offset) += src
|
|
|
|
In addition to the simple atomic operations, there also is a modifier and
|
|
two complex atomic operations:
|
|
|
|
=========== ================ ===========================
|
|
imm value description
|
|
=========== ================ ===========================
|
|
BPF_FETCH 0x01 modifier: return old value
|
|
BPF_XCHG 0xe0 | BPF_FETCH atomic exchange
|
|
BPF_CMPXCHG 0xf0 | BPF_FETCH atomic compare and exchange
|
|
=========== ================ ===========================
|
|
|
|
The ``BPF_FETCH`` modifier is optional for simple atomic operations, and
|
|
always set for the complex atomic operations. If the ``BPF_FETCH`` flag
|
|
is set, then the operation also overwrites ``src`` with the value that
|
|
was in memory before it was modified.
|
|
|
|
The ``BPF_XCHG`` operation atomically exchanges ``src`` with the value
|
|
addressed by ``dst + offset``.
|
|
|
|
The ``BPF_CMPXCHG`` operation atomically compares the value addressed by
|
|
``dst + offset`` with ``R0``. If they match, the value addressed by
|
|
``dst + offset`` is replaced with ``src``. In either case, the
|
|
value that was at ``dst + offset`` before the operation is zero-extended
|
|
and loaded back to ``R0``.
|
|
|
|
64-bit immediate instructions
|
|
-----------------------------
|
|
|
|
Instructions with the ``BPF_IMM`` 'mode' modifier use the wide instruction
|
|
encoding defined in `Instruction encoding`_, and use the 'src' field of the
|
|
basic instruction to hold an opcode subtype.
|
|
|
|
The following table defines a set of ``BPF_IMM | BPF_DW | BPF_LD`` instructions
|
|
with opcode subtypes in the 'src' field, using new terms such as "map"
|
|
defined further below:
|
|
|
|
========================= ====== === ========================================= =========== ==============
|
|
opcode construction opcode src pseudocode imm type dst type
|
|
========================= ====== === ========================================= =========== ==============
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x0 dst = imm64 integer integer
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x1 dst = map_by_fd(imm) map fd map
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x2 dst = map_val(map_by_fd(imm)) + next_imm map fd data pointer
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x3 dst = var_addr(imm) variable id data pointer
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x4 dst = code_addr(imm) integer code pointer
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x5 dst = map_by_idx(imm) map index map
|
|
BPF_IMM | BPF_DW | BPF_LD 0x18 0x6 dst = map_val(map_by_idx(imm)) + next_imm map index data pointer
|
|
========================= ====== === ========================================= =========== ==============
|
|
|
|
where
|
|
|
|
* map_by_fd(imm) means to convert a 32-bit file descriptor into an address of a map (see `Maps`_)
|
|
* map_by_idx(imm) means to convert a 32-bit index into an address of a map
|
|
* map_val(map) gets the address of the first value in a given map
|
|
* var_addr(imm) gets the address of a platform variable (see `Platform Variables`_) with a given id
|
|
* code_addr(imm) gets the address of the instruction at a specified relative offset in number of (64-bit) instructions
|
|
* the 'imm type' can be used by disassemblers for display
|
|
* the 'dst type' can be used for verification and JIT compilation purposes
|
|
|
|
Maps
|
|
~~~~
|
|
|
|
Maps are shared memory regions accessible by BPF programs on some platforms.
|
|
A map can have various semantics as defined in a separate document, and may or
|
|
may not have a single contiguous memory region, but the 'map_val(map)' is
|
|
currently only defined for maps that do have a single contiguous memory region.
|
|
|
|
Each map can have a file descriptor (fd) if supported by the platform, where
|
|
'map_by_fd(imm)' means to get the map with the specified file descriptor. Each
|
|
BPF program can also be defined to use a set of maps associated with the
|
|
program at load time, and 'map_by_idx(imm)' means to get the map with the given
|
|
index in the set associated with the BPF program containing the instruction.
|
|
|
|
Platform Variables
|
|
~~~~~~~~~~~~~~~~~~
|
|
|
|
Platform variables are memory regions, identified by integer ids, exposed by
|
|
the runtime and accessible by BPF programs on some platforms. The
|
|
'var_addr(imm)' operation means to get the address of the memory region
|
|
identified by the given id.
|
|
|
|
Legacy BPF Packet access instructions
|
|
-------------------------------------
|
|
|
|
BPF previously introduced special instructions for access to packet data that were
|
|
carried over from classic BPF. However, these instructions are
|
|
deprecated and should no longer be used.
|