10615907e9
This add frame DMA functionality to the Sparx5 platform. Ethernet frames can be extracted or injected autonomously to or from the device’s DDR3/DDR3L memory and/or PCIe memory space. Linked list data structures in memory are used for injecting or extracting Ethernet frames. The FDMA generates interrupts when frame extraction or injection is done and when the linked lists need updating. The FDMA implements two extraction channels, one per switch core port towards the VCore CPU system and a total of six injection channels. Extraction channels are mapped one-to-one to the CPU ports, while injection channels can be individually assigned to any CPU port. - FDMA channel 0 through 5 corresponds to CPU port 0 injection direction FDMA_CH_CFG[channel].CH_INJ_PORT is set to 0. - FDMA channel 0 through 5 corresponds to CPU port 1 injection direction when FDMA_CH_CFG[channel].CH_INJ_PORT is set to 1. - FDMA channel 6 corresponds to CPU port 0 extraction direction. - FDMA channel 7 corresponds to CPU port 1 extraction direction. The FDMA implements a strict priority scheme among channels. Extraction channels are prioritized over injection channels and secondarily channels with higher channel number are prioritized over channels with lower number. On the other hand, ports are being served on an equal-bandwidth principle both on injection and extraction directions. The equal-bandwidth principle will not force an equal bandwidth. Instead, it ensures that the ports perform at their best considering the operating conditions. When more than one injection channel is enabled for injection on the same CPU port, priority determines which channel can inject data. Ownership is re-arbitrated on frame boundaries. The FDMA processes linked lists of DMA Control Block Structures (DCBs). The DCBs have the same basic structure for both injection and extraction. A DCB must be placed on a 64-bit word-aligned address in memory. Each DCB has a per-channel configurable amount of associated data blocks in memory, where the frame data is stored. The data blocks that are used by extraction channels must be placed on 64-bit word aligned addresses in memory, and their length must be a multiple of 128 bytes. A DCB carries the pointer to the next DCB of the linked list, the INFO word which holds information for the DCB, and a pair of status word and memory pointer for every data block that it is associated with. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
95 lines
2.1 KiB
C
95 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Microchip Sparx5 Switch driver
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*
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* Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
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*/
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#ifndef __SPARX5_PORT_H__
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#define __SPARX5_PORT_H__
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#include "sparx5_main.h"
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static inline bool sparx5_port_is_2g5(int portno)
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{
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return portno >= 16 && portno <= 47;
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}
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static inline bool sparx5_port_is_5g(int portno)
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{
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return portno <= 11 || portno == 64;
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}
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static inline bool sparx5_port_is_10g(int portno)
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{
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return (portno >= 12 && portno <= 15) || (portno >= 48 && portno <= 55);
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}
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static inline bool sparx5_port_is_25g(int portno)
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{
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return portno >= 56 && portno <= 63;
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}
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static inline u32 sparx5_to_high_dev(int port)
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{
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if (sparx5_port_is_5g(port))
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return TARGET_DEV5G;
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if (sparx5_port_is_10g(port))
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return TARGET_DEV10G;
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return TARGET_DEV25G;
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}
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static inline u32 sparx5_to_pcs_dev(int port)
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{
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if (sparx5_port_is_5g(port))
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return TARGET_PCS5G_BR;
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if (sparx5_port_is_10g(port))
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return TARGET_PCS10G_BR;
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return TARGET_PCS25G_BR;
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}
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static inline int sparx5_port_dev_index(int port)
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{
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if (sparx5_port_is_2g5(port))
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return port;
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if (sparx5_port_is_5g(port))
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return (port <= 11 ? port : 12);
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if (sparx5_port_is_10g(port))
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return (port >= 12 && port <= 15) ?
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port - 12 : port - 44;
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return (port - 56);
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}
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int sparx5_port_init(struct sparx5 *sparx5,
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struct sparx5_port *spx5_port,
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struct sparx5_port_config *conf);
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int sparx5_port_config(struct sparx5 *sparx5,
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struct sparx5_port *spx5_port,
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struct sparx5_port_config *conf);
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int sparx5_port_pcs_set(struct sparx5 *sparx5,
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struct sparx5_port *port,
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struct sparx5_port_config *conf);
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int sparx5_serdes_set(struct sparx5 *sparx5,
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struct sparx5_port *spx5_port,
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struct sparx5_port_config *conf);
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struct sparx5_port_status {
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bool link;
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bool link_down;
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int speed;
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bool an_complete;
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int duplex;
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int pause;
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};
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int sparx5_get_port_status(struct sparx5 *sparx5,
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struct sparx5_port *port,
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struct sparx5_port_status *status);
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void sparx5_port_enable(struct sparx5_port *port, bool enable);
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int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed);
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#endif /* __SPARX5_PORT_H__ */
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