a30a555d74
Transforms the bcm-2835 native SPI-chip select to their gpio-cs equivalent.
This allows for some support of some optimizations that are not
possible due to HW-gliches on the CS line - especially filling
the FIFO before enabling SPI interrupts (by writing to CS register)
while the transfer is already in progress (See commit: e3a2be3030)
This patch also works arround some issues in bcm2835-pinctrl which does not
set the value when setting the GPIO as output - it just sets up output and
(typically) leaves the GPIO as low. When a fix for this is merged then this
gpio_set_value can get removed from bcm2835_spi_setup.
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
459 lines
13 KiB
C
459 lines
13 KiB
C
/*
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* Driver for Broadcom BCM2835 SPI Controllers
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*
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* Copyright (C) 2012 Chris Boot
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* Copyright (C) 2013 Stephen Warren
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* Copyright (C) 2015 Martin Sperl
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*
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* This driver is inspired by:
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* spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
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* spi-atmel.c, Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_gpio.h>
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#include <linux/of_device.h>
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#include <linux/spi/spi.h>
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/* SPI register offsets */
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#define BCM2835_SPI_CS 0x00
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#define BCM2835_SPI_FIFO 0x04
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#define BCM2835_SPI_CLK 0x08
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#define BCM2835_SPI_DLEN 0x0c
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#define BCM2835_SPI_LTOH 0x10
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#define BCM2835_SPI_DC 0x14
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/* Bitfields in CS */
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#define BCM2835_SPI_CS_LEN_LONG 0x02000000
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#define BCM2835_SPI_CS_DMA_LEN 0x01000000
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#define BCM2835_SPI_CS_CSPOL2 0x00800000
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#define BCM2835_SPI_CS_CSPOL1 0x00400000
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#define BCM2835_SPI_CS_CSPOL0 0x00200000
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#define BCM2835_SPI_CS_RXF 0x00100000
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#define BCM2835_SPI_CS_RXR 0x00080000
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#define BCM2835_SPI_CS_TXD 0x00040000
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#define BCM2835_SPI_CS_RXD 0x00020000
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#define BCM2835_SPI_CS_DONE 0x00010000
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#define BCM2835_SPI_CS_LEN 0x00002000
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#define BCM2835_SPI_CS_REN 0x00001000
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#define BCM2835_SPI_CS_ADCS 0x00000800
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#define BCM2835_SPI_CS_INTR 0x00000400
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#define BCM2835_SPI_CS_INTD 0x00000200
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#define BCM2835_SPI_CS_DMAEN 0x00000100
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#define BCM2835_SPI_CS_TA 0x00000080
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#define BCM2835_SPI_CS_CSPOL 0x00000040
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#define BCM2835_SPI_CS_CLEAR_RX 0x00000020
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#define BCM2835_SPI_CS_CLEAR_TX 0x00000010
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#define BCM2835_SPI_CS_CPOL 0x00000008
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#define BCM2835_SPI_CS_CPHA 0x00000004
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#define BCM2835_SPI_CS_CS_10 0x00000002
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#define BCM2835_SPI_CS_CS_01 0x00000001
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#define BCM2835_SPI_TIMEOUT_MS 30000
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#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_NO_CS | SPI_3WIRE)
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#define DRV_NAME "spi-bcm2835"
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struct bcm2835_spi {
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void __iomem *regs;
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struct clk *clk;
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int irq;
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const u8 *tx_buf;
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u8 *rx_buf;
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int tx_len;
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int rx_len;
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};
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static inline u32 bcm2835_rd(struct bcm2835_spi *bs, unsigned reg)
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{
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return readl(bs->regs + reg);
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}
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static inline void bcm2835_wr(struct bcm2835_spi *bs, unsigned reg, u32 val)
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{
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writel(val, bs->regs + reg);
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}
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static inline void bcm2835_rd_fifo(struct bcm2835_spi *bs)
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{
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u8 byte;
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while ((bs->rx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_RXD)) {
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byte = bcm2835_rd(bs, BCM2835_SPI_FIFO);
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if (bs->rx_buf)
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*bs->rx_buf++ = byte;
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bs->rx_len--;
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}
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}
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static inline void bcm2835_wr_fifo(struct bcm2835_spi *bs)
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{
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u8 byte;
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while ((bs->tx_len) &&
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(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_TXD)) {
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byte = bs->tx_buf ? *bs->tx_buf++ : 0;
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bcm2835_wr(bs, BCM2835_SPI_FIFO, byte);
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bs->tx_len--;
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}
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}
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static void bcm2835_spi_reset_hw(struct spi_master *master)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* Disable SPI interrupts and transfer */
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cs &= ~(BCM2835_SPI_CS_INTR |
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BCM2835_SPI_CS_INTD |
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BCM2835_SPI_CS_TA);
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/* and reset RX/TX FIFOS */
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cs |= BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX;
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/* and reset the SPI_HW */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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}
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static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
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{
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struct spi_master *master = dev_id;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* Read as many bytes as possible from FIFO */
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bcm2835_rd_fifo(bs);
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/* Write as many bytes as possible to FIFO */
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bcm2835_wr_fifo(bs);
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/* based on flags decide if we can finish the transfer */
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if (bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE) {
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/* Transfer complete - reset SPI HW */
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bcm2835_spi_reset_hw(master);
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/* wake up the framework */
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complete(&master->xfer_completion);
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}
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return IRQ_HANDLED;
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}
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static int bcm2835_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *tfr)
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{
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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unsigned long spi_hz, clk_hz, cdiv;
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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/* set clock */
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spi_hz = tfr->speed_hz;
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clk_hz = clk_get_rate(bs->clk);
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if (spi_hz >= clk_hz / 2) {
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cdiv = 2; /* clk_hz/2 is the fastest we can go */
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} else if (spi_hz) {
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/* CDIV must be a multiple of two */
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cdiv = DIV_ROUND_UP(clk_hz, spi_hz);
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cdiv += (cdiv % 2);
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if (cdiv >= 65536)
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cdiv = 0; /* 0 is the slowest we can go */
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} else {
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cdiv = 0; /* 0 is the slowest we can go */
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}
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bcm2835_wr(bs, BCM2835_SPI_CLK, cdiv);
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/* handle all the modes */
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if ((spi->mode & SPI_3WIRE) && (tfr->rx_buf))
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cs |= BCM2835_SPI_CS_REN;
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if (spi->mode & SPI_CPOL)
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cs |= BCM2835_SPI_CS_CPOL;
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if (spi->mode & SPI_CPHA)
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cs |= BCM2835_SPI_CS_CPHA;
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/* for gpio_cs set dummy CS so that no HW-CS get changed
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* we can not run this in bcm2835_spi_set_cs, as it does
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* not get called for cs_gpio cases, so we need to do it here
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*/
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if (gpio_is_valid(spi->cs_gpio) || (spi->mode & SPI_NO_CS))
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cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
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/* set transmit buffers and length */
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bs->tx_buf = tfr->tx_buf;
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bs->rx_buf = tfr->rx_buf;
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bs->tx_len = tfr->len;
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bs->rx_len = tfr->len;
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/* fill in fifo if we have gpio-cs
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* note that there have been rare events where the native-CS
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* flapped for <1us which may change the behaviour
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* with gpio-cs this does not happen, so it is implemented
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* only for this case
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*/
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if (gpio_is_valid(spi->cs_gpio)) {
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/* enable HW block, but without interrupts enabled
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* this would triggern an immediate interrupt
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*/
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bcm2835_wr(bs, BCM2835_SPI_CS,
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cs | BCM2835_SPI_CS_TA);
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/* fill in tx fifo as much as possible */
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bcm2835_wr_fifo(bs);
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}
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/*
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* Enable the HW block. This will immediately trigger a DONE (TX
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* empty) interrupt, upon which we will fill the TX FIFO with the
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* first TX bytes. Pre-filling the TX FIFO here to avoid the
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* interrupt doesn't work:-(
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*/
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cs |= BCM2835_SPI_CS_INTR | BCM2835_SPI_CS_INTD | BCM2835_SPI_CS_TA;
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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/* signal that we need to wait for completion */
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return 1;
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}
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static void bcm2835_spi_handle_err(struct spi_master *master,
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struct spi_message *msg)
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{
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bcm2835_spi_reset_hw(master);
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}
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static void bcm2835_spi_set_cs(struct spi_device *spi, bool gpio_level)
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{
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/*
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* we can assume that we are "native" as per spi_set_cs
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* calling us ONLY when cs_gpio is not set
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* we can also assume that we are CS < 3 as per bcm2835_spi_setup
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* we would not get called because of error handling there.
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* the level passed is the electrical level not enabled/disabled
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* so it has to get translated back to enable/disable
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* see spi_set_cs in spi.c for the implementation
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*/
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struct spi_master *master = spi->master;
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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u32 cs = bcm2835_rd(bs, BCM2835_SPI_CS);
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bool enable;
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/* calculate the enable flag from the passed gpio_level */
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enable = (spi->mode & SPI_CS_HIGH) ? gpio_level : !gpio_level;
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/* set flags for "reverse" polarity in the registers */
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if (spi->mode & SPI_CS_HIGH) {
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/* set the correct CS-bits */
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cs |= BCM2835_SPI_CS_CSPOL;
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cs |= BCM2835_SPI_CS_CSPOL0 << spi->chip_select;
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} else {
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/* clean the CS-bits */
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cs &= ~BCM2835_SPI_CS_CSPOL;
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cs &= ~(BCM2835_SPI_CS_CSPOL0 << spi->chip_select);
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}
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/* select the correct chip_select depending on disabled/enabled */
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if (enable) {
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/* set cs correctly */
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if (spi->mode & SPI_NO_CS) {
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/* use the "undefined" chip-select */
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cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
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} else {
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/* set the chip select */
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cs &= ~(BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01);
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cs |= spi->chip_select;
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}
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} else {
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/* disable CSPOL which puts HW-CS into deselected state */
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cs &= ~BCM2835_SPI_CS_CSPOL;
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/* use the "undefined" chip-select as precaution */
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cs |= BCM2835_SPI_CS_CS_10 | BCM2835_SPI_CS_CS_01;
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}
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/* finally set the calculated flags in SPI_CS */
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bcm2835_wr(bs, BCM2835_SPI_CS, cs);
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}
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static int chip_match_name(struct gpio_chip *chip, void *data)
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{
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return !strcmp(chip->label, data);
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}
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static int bcm2835_spi_setup(struct spi_device *spi)
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{
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int err;
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struct gpio_chip *chip;
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/*
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* sanity checking the native-chipselects
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*/
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if (spi->mode & SPI_NO_CS)
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return 0;
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if (gpio_is_valid(spi->cs_gpio))
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return 0;
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if (spi->chip_select > 1) {
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/* error in the case of native CS requested with CS > 1
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* officially there is a CS2, but it is not documented
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* which GPIO is connected with that...
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*/
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dev_err(&spi->dev,
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"setup: only two native chip-selects are supported\n");
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return -EINVAL;
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}
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/* now translate native cs to GPIO */
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/* get the gpio chip for the base */
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chip = gpiochip_find("pinctrl-bcm2835", chip_match_name);
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if (!chip)
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return 0;
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/* and calculate the real CS */
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spi->cs_gpio = chip->base + 8 - spi->chip_select;
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/* and set up the "mode" and level */
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dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n",
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spi->chip_select, spi->cs_gpio);
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/* set up GPIO as output and pull to the correct level */
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err = gpio_direction_output(spi->cs_gpio,
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(spi->mode & SPI_CS_HIGH) ? 0 : 1);
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if (err) {
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dev_err(&spi->dev,
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"could not set CS%i gpio %i as output: %i",
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spi->chip_select, spi->cs_gpio, err);
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return err;
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}
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/* the implementation of pinctrl-bcm2835 currently does not
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* set the GPIO value when using gpio_direction_output
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* so we are setting it here explicitly
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*/
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gpio_set_value(spi->cs_gpio, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
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return 0;
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}
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static int bcm2835_spi_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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struct bcm2835_spi *bs;
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struct resource *res;
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int err;
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master = spi_alloc_master(&pdev->dev, sizeof(*bs));
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if (!master) {
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dev_err(&pdev->dev, "spi_alloc_master() failed\n");
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return -ENOMEM;
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}
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platform_set_drvdata(pdev, master);
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master->mode_bits = BCM2835_SPI_MODE_BITS;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->num_chipselect = 3;
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master->setup = bcm2835_spi_setup;
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master->set_cs = bcm2835_spi_set_cs;
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master->transfer_one = bcm2835_spi_transfer_one;
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master->handle_err = bcm2835_spi_handle_err;
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master->dev.of_node = pdev->dev.of_node;
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bs = spi_master_get_devdata(master);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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bs->regs = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(bs->regs)) {
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err = PTR_ERR(bs->regs);
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goto out_master_put;
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}
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bs->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(bs->clk)) {
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err = PTR_ERR(bs->clk);
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dev_err(&pdev->dev, "could not get clk: %d\n", err);
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goto out_master_put;
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}
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bs->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
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if (bs->irq <= 0) {
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dev_err(&pdev->dev, "could not get IRQ: %d\n", bs->irq);
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err = bs->irq ? bs->irq : -ENODEV;
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goto out_master_put;
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}
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clk_prepare_enable(bs->clk);
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err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
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dev_name(&pdev->dev), master);
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if (err) {
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dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
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goto out_clk_disable;
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}
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/* initialise the hardware with the default polarities */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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err = devm_spi_register_master(&pdev->dev, master);
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if (err) {
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dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
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goto out_clk_disable;
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}
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return 0;
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out_clk_disable:
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clk_disable_unprepare(bs->clk);
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out_master_put:
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spi_master_put(master);
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return err;
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}
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static int bcm2835_spi_remove(struct platform_device *pdev)
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{
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struct spi_master *master = platform_get_drvdata(pdev);
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struct bcm2835_spi *bs = spi_master_get_devdata(master);
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/* Clear FIFOs, and disable the HW block */
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bcm2835_wr(bs, BCM2835_SPI_CS,
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BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);
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clk_disable_unprepare(bs->clk);
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return 0;
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}
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static const struct of_device_id bcm2835_spi_match[] = {
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{ .compatible = "brcm,bcm2835-spi", },
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{}
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};
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MODULE_DEVICE_TABLE(of, bcm2835_spi_match);
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static struct platform_driver bcm2835_spi_driver = {
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.driver = {
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.name = DRV_NAME,
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.of_match_table = bcm2835_spi_match,
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},
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.probe = bcm2835_spi_probe,
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|
.remove = bcm2835_spi_remove,
|
|
};
|
|
module_platform_driver(bcm2835_spi_driver);
|
|
|
|
MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2835");
|
|
MODULE_AUTHOR("Chris Boot <bootc@bootc.net>");
|
|
MODULE_LICENSE("GPL v2");
|