Rasmus Villemoes
a34e0353a6
spi: spi-imx: fix mixing of native and gpio chipselects for imx51/imx53/imx6 variants
Commit 87c614175bbf (spi: spi-imx: fix MX51_ECSPI_* macros when cs > 3) ensured that the argument passed to the macros was masked with &3, so that we no longer write outside the intended fields in the various control registers. When all chip selects are gpios, this works just fine. However, when a mix of native and gpio chip selects are in use, that masking is too naive. Say, for example, that SS0 is muxed as native chip select, and there is also a chip at 4 (obviously with a gpio cs). In that case, when accessing the latter chip, both the SS0 pin and the gpio pin will be asserted low. The fix for this is to use the ->unused_native_cs value as channel number for any spi device which uses a gpio as chip select. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Link: https://lore.kernel.org/r/20230602115731.708883-1-linux@rasmusvillemoes.dk Signed-off-by: Mark Brown <broonie@kernel.org>
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