ca8df97fe6
The RISC-V advanced platform-level interrupt controller (APLIC) has two modes of operation: 1) Direct mode and 2) MSI mode. (For more details, refer https://github.com/riscv/riscv-aia) In APLIC MSI-mode, wired interrupts are forwared as message signaled interrupts (MSIs) to CPUs via IMSIC. Extend the existing APLIC irqchip driver to support MSI-mode for RISC-V platforms having both wired interrupts and MSIs. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Björn Töpel <bjorn@rivosinc.com> Reviewed-by: Björn Töpel <bjorn@rivosinc.com> Link: https://lore.kernel.org/r/20240307140307.646078-8-apatel@ventanamicro.com
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Western Digital Corporation or its affiliates.
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#ifndef _IRQ_RISCV_APLIC_MAIN_H
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#define _IRQ_RISCV_APLIC_MAIN_H
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/fwnode.h>
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#define APLIC_DEFAULT_PRIORITY 1
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struct aplic_msicfg {
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phys_addr_t base_ppn;
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u32 hhxs;
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u32 hhxw;
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u32 lhxs;
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u32 lhxw;
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};
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struct aplic_priv {
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struct device *dev;
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u32 gsi_base;
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u32 nr_irqs;
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u32 nr_idcs;
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void __iomem *regs;
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struct aplic_msicfg msicfg;
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};
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void aplic_irq_unmask(struct irq_data *d);
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void aplic_irq_mask(struct irq_data *d);
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int aplic_irq_set_type(struct irq_data *d, unsigned int type);
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int aplic_irqdomain_translate(struct irq_fwspec *fwspec, u32 gsi_base,
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unsigned long *hwirq, unsigned int *type);
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void aplic_init_hw_global(struct aplic_priv *priv, bool msi_mode);
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int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs);
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int aplic_direct_setup(struct device *dev, void __iomem *regs);
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#ifdef CONFIG_RISCV_APLIC_MSI
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int aplic_msi_setup(struct device *dev, void __iomem *regs);
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#else
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static inline int aplic_msi_setup(struct device *dev, void __iomem *regs)
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{
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return -ENODEV;
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}
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#endif
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#endif
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