Christoph Hellwig a4c3733d32 riscv: abstract out CSR names for supervisor vs machine mode ...

Many of the privileged CSRs exist in a supervisor and machine version
that are used very similarly.  Provide versions of the CSR names and
fields that map to either the S-mode or M-mode variant depending on
a new CONFIG_RISCV_M_MODE kconfig symbol.

Contains contributions from Damien Le Moal <Damien.LeMoal@wdc.com>
and Paul Walmsley <paul.walmsley@sifive.com>.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource, drivers/irqchip
[paul.walmsley@sifive.com: updated to apply]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

2019-11-05 09:20:42 -08:00

..

cacheflush.c

riscv: cleanup riscv_cpuid_to_hartid_mask

2019-09-05 01:51:57 -07:00

context.c

riscv: add missing header file includes

2019-10-28 00:46:01 -07:00

extable.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

fault.c

riscv: abstract out CSR names for supervisor vs machine mode

2019-11-05 09:20:42 -08:00

hugetlbpage.c

riscv: Introduce huge page support for 32/64bit kernel

2019-07-03 15:23:38 -07:00

init.c

riscv: init: merge split string literals in preprocessor directive

2019-10-28 00:46:01 -07:00

ioremap.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286

2019-06-05 17:36:37 +02:00

Makefile

riscv: move the TLB flush logic out of line

2019-09-05 01:54:51 -07:00

sifive_l2_cache.c

riscv: mark some code and data as file-static

2019-10-28 00:46:01 -07:00

tlbflush.c

riscv: move the TLB flush logic out of line

2019-09-05 01:54:51 -07:00