799c5b9cb9
[WHY] This change was made because DTO programming was double-buffered, which is itself an issue. After deactivating the DTO double buffer, this change becomes unnecessary. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/slab.h>
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dcn20_dccg.h"
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#define TO_DCN_DCCG(dccg)\
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container_of(dccg, struct dcn_dccg, base)
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#define REG(reg) \
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(dccg_dcn->regs->reg)
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#undef FN
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#define FN(reg_name, field_name) \
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dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
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#define CTX \
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dccg_dcn->base.ctx
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#define DC_LOGGER \
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dccg->ctx->logger
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void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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if (dccg->ref_dppclk && req_dppclk) {
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int ref_dppclk = dccg->ref_dppclk;
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ASSERT(req_dppclk <= ref_dppclk);
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/* need to clamp to 8 bits */
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if (ref_dppclk > 0xff) {
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int divider = (ref_dppclk + 0xfe) / 0xff;
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ref_dppclk /= divider;
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req_dppclk = (req_dppclk + divider - 1) / divider;
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if (req_dppclk > ref_dppclk)
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req_dppclk = ref_dppclk;
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}
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REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
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DPPCLK0_DTO_PHASE, req_dppclk,
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DPPCLK0_DTO_MODULO, ref_dppclk);
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REG_UPDATE(DPPCLK_DTO_CTRL,
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DPPCLK_DTO_ENABLE[dpp_inst], 1);
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} else {
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REG_UPDATE(DPPCLK_DTO_CTRL,
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DPPCLK_DTO_ENABLE[dpp_inst], 0);
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}
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}
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void dccg2_get_dccg_ref_freq(struct dccg *dccg,
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unsigned int xtalin_freq_inKhz,
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unsigned int *dccg_ref_freq_inKhz)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
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uint32_t clk_en = 0;
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uint32_t clk_sel = 0;
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REG_GET_2(REFCLK_CNTL, REFCLK_CLOCK_EN, &clk_en, REFCLK_SRC_SEL, &clk_sel);
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if (clk_en != 0) {
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// DCN20 has never been validated for non-xtalin as reference
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// frequency. There's actually no way for DC to determine what
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// frequency a non-xtalin source is.
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ASSERT_CRITICAL(false);
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}
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*dccg_ref_freq_inKhz = xtalin_freq_inKhz;
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return;
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}
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void dccg2_init(struct dccg *dccg)
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{
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}
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static const struct dccg_funcs dccg2_funcs = {
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.update_dpp_dto = dccg2_update_dpp_dto,
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.get_dccg_ref_freq = dccg2_get_dccg_ref_freq,
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.dccg_init = dccg2_init
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};
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struct dccg *dccg2_create(
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struct dc_context *ctx,
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const struct dccg_registers *regs,
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const struct dccg_shift *dccg_shift,
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const struct dccg_mask *dccg_mask)
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{
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struct dcn_dccg *dccg_dcn = kzalloc(sizeof(*dccg_dcn), GFP_KERNEL);
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struct dccg *base;
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if (dccg_dcn == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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base = &dccg_dcn->base;
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base->ctx = ctx;
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base->funcs = &dccg2_funcs;
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dccg_dcn->regs = regs;
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dccg_dcn->dccg_shift = dccg_shift;
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dccg_dcn->dccg_mask = dccg_mask;
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return &dccg_dcn->base;
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}
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void dcn_dccg_destroy(struct dccg **dccg)
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{
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struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(*dccg);
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kfree(dccg_dcn);
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*dccg = NULL;
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}
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