Pierre-Louis Bossart a50477e55f ASoC: Intel: cht_bsw_rt5645: add Baytrail MCLK support
The existing code assumes a 19.2 MHz MCLK as the default
hardware configuration. This is valid for CherryTrail but
not for Baytrail.

Add explicit MCLK configuration to set the 19.2 clock on/off
depending on DAPM events.

This is a prerequisite step to enable devices with Baytrail
and RT5645 such as Asus X205TA

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2017-01-31 20:03:56 +00:00
..
2016-10-07 20:19:31 -07:00
2016-12-25 17:21:22 +01:00
2016-12-25 17:21:22 +01:00
2016-12-25 17:21:22 +01:00
2017-01-24 16:24:18 +00:00
2016-12-14 11:14:28 -08:00
2016-10-07 20:19:31 -07:00
2016-12-25 17:21:22 +01:00
2016-01-20 09:59:27 +01:00
2015-08-31 16:25:22 +02:00