Sowjanya Komatineni f8c9dd2b82 media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes ... Tegra VI/CSI hardware don't have native 8 lane CSI RX port. But x8 capture can be supported by using consecutive x4 ports simultaneously with HDMI-to-CSI bridges where source image is split on to two x4 ports. This patch updates dt-bindings for csi endpoint data-lane property with maximum of 8 lanes. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>		2021-01-04 13:02:44 +01:00
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nvidia,tegra20-host1x.txt	media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes	2021-01-04 13:02:44 +01:00
nvidia,tegra114-mipi.txt