9eaad15e5a
Add the compatible string for SM8350 SoC from Qualcomm. Signed-off-by: Vinod Koul <vkoul@kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210115090941.2289416-2-vkoul@kernel.org
76 lines
2.4 KiB
Plaintext
76 lines
2.4 KiB
Plaintext
PDC interrupt controller
|
|
|
|
Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
|
|
Power Domain Controller (PDC) that is on always-on domain. In addition to
|
|
providing power control for the power domains, the hardware also has an
|
|
interrupt controller that can be used to help detect edge low interrupts as
|
|
well detect interrupts when the GIC is non-operational.
|
|
|
|
GIC is parent interrupt controller at the highest level. Platform interrupt
|
|
controller PDC is next in hierarchy, followed by others. Drivers requiring
|
|
wakeup capabilities of their device interrupts routed through the PDC, must
|
|
specify PDC as their interrupt controller and request the PDC port associated
|
|
with the GIC interrupt. See example below.
|
|
|
|
Properties:
|
|
|
|
- compatible:
|
|
Usage: required
|
|
Value type: <string>
|
|
Definition: Should contain "qcom,<soc>-pdc" and "qcom,pdc"
|
|
- "qcom,sc7180-pdc": For SC7180
|
|
- "qcom,sdm845-pdc": For SDM845
|
|
- "qcom,sdm8250-pdc": For SM8250
|
|
- "qcom,sdm8350-pdc": For SM8350
|
|
|
|
- reg:
|
|
Usage: required
|
|
Value type: <prop-encoded-array>
|
|
Definition: Specifies the base physical address for PDC hardware.
|
|
|
|
- interrupt-cells:
|
|
Usage: required
|
|
Value type: <u32>
|
|
Definition: Specifies the number of cells needed to encode an interrupt
|
|
source.
|
|
Must be 2.
|
|
The first element of the tuple is the PDC pin for the
|
|
interrupt.
|
|
The second element is the trigger type.
|
|
|
|
- interrupt-controller:
|
|
Usage: required
|
|
Value type: <bool>
|
|
Definition: Identifies the node as an interrupt controller.
|
|
|
|
- qcom,pdc-ranges:
|
|
Usage: required
|
|
Value type: <u32 array>
|
|
Definition: Specifies the PDC pin offset and the number of PDC ports.
|
|
The tuples indicates the valid mapping of valid PDC ports
|
|
and their hwirq mapping.
|
|
The first element of the tuple is the starting PDC port.
|
|
The second element is the GIC hwirq number for the PDC port.
|
|
The third element is the number of interrupts in sequence.
|
|
|
|
Example:
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sdm845-pdc";
|
|
reg = <0xb220000 0x30000>;
|
|
qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
DT binding of a device that wants to use the GIC SPI 514 as a wakeup
|
|
interrupt, must do -
|
|
|
|
wake-device {
|
|
interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
In this case interrupt 514 would be mapped to port 2 on the PDC as defined by
|
|
the qcom,pdc-ranges property.
|