e533cda12d
As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board -----BEGIN PGP SIGNATURE----- iQJDBAABCgAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl+TVacPHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx37MMP/imMO5e0QY1/7xxXWm4Kgc/Uffqw2Dvhj74a 4Nrudwz6oUFGpZzIFYxqeCeWwotjA0nXmvM4Nl/SbxtlbV6nY/JrOL1OJToaGY0z Oc1jdA0MdXITdi6Xl5PTRqDeIHTSUmTclZWi5gvT7LFEvHog3mquJ7PiNTrjyuV0 9BmHipwfmH6V5gDJZvN2dDlkhy0cpQKJFw7ylKCL89UNiEAd2QtNG0d0RLdz7yPX IGdecFelOhG9MSZyuFYYB2HOI33ukjZ9dA+yFy7BWOqegf/Z5hI02mxpke7Sys/5 4XEN7ksSSYr6sm3h9XNW++IYkapZ9y/ZW+sQdiBZ3GMOwMXj02TdRkpC7f+FgAPo Hl7yXodGmXynL6ULu7/lIbBvqfWkLcwfVCYZx6PoWRE2q5g5ifoYp9b8kI5cLXrb BJn85XIuIaoO0cgrq7EzZnksaiwY1CNL84mYgkKRCGbBoJKHRiU+8Ilm5SKzk3kq KJ0gmbwFMjvTYxs3g6LPCo0jUNLjmLQMr0tL7iHDWkk5uqA+gfjKSLQfPby3jrMr 6RDZBzMB+tPz1e++RWo41XD/Mm2kw8MGstsCOLzk2TdLh7e3fPfU4g7m0aqs/Q1y +LCqshffF/XVzV2uTFHDUGWufIM9nY6rdzuBc+JACJ5E+QyDg1tGKtMB3TYqgdN2 aRY3NLSv =xjfB -----END PGP SIGNATURE----- Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM Devicetree updates from Olof Johansson: "As usual, most of the changes are to devicetrees. Besides smaller fixes, some refactorings and cleanups, some of the new platforms and chips (or significant features) supported are below: Broadcom boards: - Cisco Meraki MR32 (BCM53016-based) - BCM2711 (RPi4) display pipeline support Actions Semi boards: - Caninos Loucos Labrador SBC (S500-based) - RoseapplePi SBC (S500-based) Allwinner SoCs/boards: - A100 SoC with Perf1 board - Mali, DMA, Cetrus and IR support for R40 SoC Amlogic boards: - Libretch S905x CC V2 board - Hardkernel ODROID-N2+ board Aspeed boards/platforms: - Wistron Mowgli (AST2500-based, Power9 OpenPower server) - Facebook Wedge400 (AST2500-based, ToR switch) Hisilicon SoC: - SD5203 SoC Nvidia boards: - Tegra234 VDK, for pre-silicon Orin SoC NXP i.MX boards: - Librem 5 phone - i.MX8MM DDR4 EVK - Variscite VAR-SOM-MX8MN SoM - Symphony board - Tolino Shine 2 HD - TQMa6 SoM - Y Soft IOTA Orion Rockchip boards: - NanoPi R2S board - A95X-Z2 board - more Rock-Pi4 variants STM32 boards: - Odyssey SOM board (STM32MP157CAC-based) - DH DRC02 board Toshiba SoCs/boards: - Visconti SoC and TPMV7708 board" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits) ARM: dts: nspire: Fix SP804 users arm64: dts: lg: Fix SP804 users arm64: dts: lg: Fix SP805 clocks ARM: mstar: Fix up the fallout from moving the dts/dtsi files ARM: mstar: Add mstar prefix to all of the dtsi/dts files ARM: mstar: Add interrupt to pm_uart ARM: mstar: Add interrupt controller to base dtsi ARM: dts: meson8: remove two invalid interrupt lines from the GPU node arm64: dts: ti: k3-j7200-common-proc-board: Add USB support arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function arm64: dts: ti: k3-j7200-main: Add USB controller arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux dt-bindings: ti-serdes-mux: Add defines for J7200 SoC ARM: dts: hisilicon: add SD5203 dts ARM: dts: hisilicon: fix the system controller compatible nodes arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1 arm64: dts: zynqmp: Remove undocumented u-boot properties arm64: dts: zynqmp: Remove additional compatible string for i2c IPs arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml ...
660 lines
16 KiB
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660 lines
16 KiB
Plaintext
/*
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* BSD LICENSE
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*
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* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/bcm-nsp.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "brcm,nsp";
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model = "Broadcom Northstar Plus SoC";
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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ethernet0 = &amac0;
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ethernet1 = &amac1;
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ethernet2 = &amac2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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enable-method = "brcm,bcm-nsp-smp";
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secondary-boot-reg = <0xffff0fec>;
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reg = <0x1>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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};
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mpcore@19000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19000000 0x00023000>;
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#address-cells = <1>;
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#size-cells = <1>;
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a9pll: arm_clk@0 {
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#clock-cells = <0>;
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compatible = "brcm,nsp-armpll";
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clocks = <&osc>;
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reg = <0x00000 0x1000>;
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};
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
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clocks = <&periph_clk>;
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};
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twd-timer@20600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_EDGE_RISING)>;
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clocks = <&periph_clk>;
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};
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twd-watchdog@20620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x20620 0x20>;
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interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x21000 0x1000>,
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<0x20100 0x100>;
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};
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L2: cache-controller@22000 {
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compatible = "arm,pl310-cache";
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reg = <0x22000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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iprocmed: iprocmed {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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iprocslow: iprocslow {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
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clock-div = <4>;
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clock-mult = <1>;
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};
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&a9pll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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axi@18000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x0011c40c>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioa: gpio@20 {
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compatible = "brcm,nsp-gpio-a";
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reg = <0x0020 0x70>,
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<0x3f1c4 0x1c>;
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#gpio-cells = <2>;
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gpio-controller;
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ngpios = <32>;
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interrupt-controller;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 0 32>;
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};
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uart0: serial@300 {
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compatible = "ns16550a";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart1: serial@400 {
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compatible = "ns16550a";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc>;
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status = "disabled";
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};
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dma: dma@20000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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dma-coherent;
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status = "disabled";
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};
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sdio: sdhci@21000 {
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compatible = "brcm,sdhci-iproc-cygnus";
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reg = <0x21000 0x100>;
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interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
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sdhci,auto-cmd12;
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clocks = <&lcpll0 BCM_NSP_LCPLL0_SDIO_CLK>;
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dma-coherent;
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status = "disabled";
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};
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amac0: ethernet@22000 {
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compatible = "brcm,nsp-amac";
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reg = <0x022000 0x1000>,
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<0x110000 0x1000>;
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reg-names = "amac_base", "idm_base";
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interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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amac1: ethernet@23000 {
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compatible = "brcm,nsp-amac";
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reg = <0x023000 0x1000>,
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<0x111000 0x1000>;
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reg-names = "amac_base", "idm_base";
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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amac2: ethernet@24000 {
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compatible = "brcm,nsp-amac";
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reg = <0x024000 0x1000>,
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<0x112000 0x1000>;
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reg-names = "amac_base", "idm_base";
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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mailbox: mailbox@25c00 {
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compatible = "brcm,iproc-fa2-mbox";
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reg = <0x25c00 0x400>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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#mbox-cells = <1>;
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brcm,rx-status-len = <32>;
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brcm,use-bcm-hdr;
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dma-coherent;
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};
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nand: nand@26000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x026000 0x600>,
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<0x11b408 0x600>,
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<0x026f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
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qspi: spi@27200 {
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compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
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reg = <0x027200 0x184>,
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<0x027000 0x124>,
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<0x11c408 0x004>,
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<0x0273a0 0x01c>;
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reg-names = "mspi", "bspi", "intr_regs",
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"intr_status_reg";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "spi_lr_fullness_reached",
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"spi_lr_session_aborted",
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"spi_lr_impatient",
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"spi_lr_session_done",
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"spi_lr_overhead",
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"mspi_done",
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"mspi_halted";
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clocks = <&iprocmed>;
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clock-names = "iprocmed";
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num-cs = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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xhci: usb@29000 {
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compatible = "generic-xhci";
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reg = <0x29000 0x1000>;
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interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb3_phy>;
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phy-names = "usb3-phy";
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dma-coherent;
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status = "disabled";
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};
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ehci0: usb@2a000 {
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compatible = "generic-ehci";
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reg = <0x2a000 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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ohci0: usb@2b000 {
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compatible = "generic-ohci";
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reg = <0x2b000 0x100>;
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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dma-coherent;
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status = "disabled";
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};
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crypto@2f000 {
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compatible = "brcm,spum-nsp-crypto";
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reg = <0x2f000 0x900>;
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mboxes = <&mailbox 0>;
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};
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gpiob: gpio@30000 {
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compatible = "brcm,iproc-nsp-gpio", "brcm,iproc-gpio";
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reg = <0x30000 0x50>;
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#gpio-cells = <2>;
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gpio-controller;
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ngpios = <4>;
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interrupt-controller;
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interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
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};
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pwm: pwm@31000 {
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compatible = "brcm,iproc-pwm";
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reg = <0x31000 0x28>;
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clocks = <&osc>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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rng: rng@33000 {
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compatible = "brcm,bcm-nsp-rng";
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reg = <0x33000 0x14>;
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};
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ccbtimer0: timer@34000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x34000 0x1000>;
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interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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clock-names = "apb_pclk";
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};
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ccbtimer1: timer@35000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x35000 0x1000>;
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interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&iprocslow>;
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clock-names = "apb_pclk";
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};
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srab: srab@36000 {
|
|
compatible = "brcm,nsp-srab";
|
|
reg = <0x36000 0x1000>,
|
|
<0x3f308 0x8>,
|
|
<0x3f410 0xc>;
|
|
reg-names = "srab", "mux_config", "sgmii";
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "link_state_p0",
|
|
"link_state_p1",
|
|
"link_state_p2",
|
|
"link_state_p3",
|
|
"link_state_p4",
|
|
"link_state_p5",
|
|
"link_state_p7",
|
|
"link_state_p8",
|
|
"phy",
|
|
"ts",
|
|
"imp_sleep_timer_p5",
|
|
"imp_sleep_timer_p7",
|
|
"imp_sleep_timer_p8";
|
|
status = "disabled";
|
|
|
|
/* ports are defined in board DTS */
|
|
};
|
|
|
|
i2c0: i2c@38000 {
|
|
compatible = "brcm,iproc-i2c";
|
|
reg = <0x38000 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clock-frequency = <100000>;
|
|
dma-coherent;
|
|
status = "disabled";
|
|
};
|
|
|
|
watchdog@39000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x39000 0x1000>;
|
|
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&iprocslow>, <&iprocslow>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
lcpll0: lcpll0@3f100 {
|
|
#clock-cells = <1>;
|
|
compatible = "brcm,nsp-lcpll0";
|
|
reg = <0x3f100 0x14>;
|
|
clocks = <&osc>;
|
|
clock-output-names = "lcpll0", "pcie_phy", "sdio",
|
|
"ddr_phy";
|
|
};
|
|
|
|
genpll: genpll@3f140 {
|
|
#clock-cells = <1>;
|
|
compatible = "brcm,nsp-genpll";
|
|
reg = <0x3f140 0x24>;
|
|
clocks = <&osc>;
|
|
clock-output-names = "genpll", "phy", "ethernetclk",
|
|
"usbclk", "iprocfast", "sata1",
|
|
"sata2";
|
|
};
|
|
|
|
pinctrl: pinctrl@3f1c0 {
|
|
compatible = "brcm,nsp-pinmux";
|
|
reg = <0x3f1c0 0x04>,
|
|
<0x30028 0x04>,
|
|
<0x3f408 0x04>;
|
|
};
|
|
|
|
thermal: thermal@3f2c0 {
|
|
compatible = "brcm,ns-thermal";
|
|
reg = <0x3f2c0 0x10>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
sata_phy: sata_phy@40100 {
|
|
compatible = "brcm,iproc-nsp-sata-phy";
|
|
reg = <0x40100 0x340>;
|
|
reg-names = "phy";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
sata_phy0: sata-phy@0 {
|
|
reg = <0>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sata_phy1: sata-phy@1 {
|
|
reg = <1>;
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
sata: ahci@41000 {
|
|
compatible = "brcm,bcm-nsp-ahci";
|
|
reg-names = "ahci", "top-ctrl";
|
|
reg = <0x41000 0x1000>, <0x40020 0x1c>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
dma-coherent;
|
|
status = "disabled";
|
|
|
|
sata0: sata-port@0 {
|
|
reg = <0>;
|
|
phys = <&sata_phy0>;
|
|
phy-names = "sata-phy";
|
|
};
|
|
|
|
sata1: sata-port@1 {
|
|
reg = <1>;
|
|
phys = <&sata_phy1>;
|
|
phy-names = "sata-phy";
|
|
};
|
|
};
|
|
|
|
usb3_phy: usb3-phy@104000 {
|
|
compatible = "brcm,ns-bx-usb3-phy";
|
|
reg = <0x104000 0x1000>,
|
|
<0x032000 0x1000>;
|
|
reg-names = "dmp", "ccb-mii";
|
|
#phy-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pcie0: pcie@18012000 {
|
|
compatible = "brcm,iproc-pcie";
|
|
reg = <0x18012000 0x1000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
linux,pci-domain = <0>;
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
|
|
/* Note: The HW does not support I/O resources. So,
|
|
* only the memory resource range is being specified.
|
|
*/
|
|
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
|
|
|
|
dma-coherent;
|
|
status = "disabled";
|
|
|
|
msi-parent = <&msi0>;
|
|
msi0: msi-controller {
|
|
compatible = "brcm,iproc-msi";
|
|
msi-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
brcm,pcie-msi-inten;
|
|
};
|
|
};
|
|
|
|
pcie1: pcie@18013000 {
|
|
compatible = "brcm,iproc-pcie";
|
|
reg = <0x18013000 0x1000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
linux,pci-domain = <1>;
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
|
|
/* Note: The HW does not support I/O resources. So,
|
|
* only the memory resource range is being specified.
|
|
*/
|
|
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
|
|
|
|
dma-coherent;
|
|
status = "disabled";
|
|
|
|
msi-parent = <&msi1>;
|
|
msi1: msi-controller {
|
|
compatible = "brcm,iproc-msi";
|
|
msi-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
brcm,pcie-msi-inten;
|
|
};
|
|
};
|
|
|
|
pcie2: pcie@18014000 {
|
|
compatible = "brcm,iproc-pcie";
|
|
reg = <0x18014000 0x1000>;
|
|
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
linux,pci-domain = <2>;
|
|
|
|
bus-range = <0x00 0xff>;
|
|
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
|
|
/* Note: The HW does not support I/O resources. So,
|
|
* only the memory resource range is being specified.
|
|
*/
|
|
ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
|
|
|
|
dma-coherent;
|
|
status = "disabled";
|
|
|
|
msi-parent = <&msi2>;
|
|
msi2: msi-controller {
|
|
compatible = "brcm,iproc-msi";
|
|
msi-controller;
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
brcm,pcie-msi-inten;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu-thermal {
|
|
polling-delay-passive = <0>;
|
|
polling-delay = <1000>;
|
|
coefficients = <(-556) 418000>;
|
|
thermal-sensors = <&thermal>;
|
|
|
|
trips {
|
|
cpu-crit {
|
|
temperature = <125000>;
|
|
hysteresis = <0>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
};
|
|
};
|
|
};
|
|
};
|