a5cadbbb08
The design is based on the exist architecture that the core will provide a uniformed way to decode the generic pin config into platform config register raw data according to the imx_cfg_params_decode maps registered by platform. Two useful macros, IMX_CFG_PARAMS_DECODE and IMX_CFG_PARAMS_DECODE_INVERT, are created for platform to register decode map conveniently. In order to cope with some special case, a platform specific fixup() function is also available to use. Note that rather than fully utilizing the generic pinconf support provided by pinctrl core, IMX only adopts the device tree bindings of generic pinconf. The config used in .pin_config_get[set] are raw register data instead of generic one which makes us align the exist using. And that's also why we cannot set pinconf_ops.is_generic. Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
98 lines
2.4 KiB
C
98 lines
2.4 KiB
C
/*
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* IMX pinmux core definitions
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*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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* Copyright (C) 2012 Linaro Ltd.
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*
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* Author: Dong Aisheng <dong.aisheng@linaro.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DRIVERS_PINCTRL_IMX_H
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#define __DRIVERS_PINCTRL_IMX_H
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#include <linux/pinctrl/pinconf-generic.h>
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struct platform_device;
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/**
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* struct imx_pin - describes a single i.MX pin
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* @pin: the pin_id of this pin
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* @mux_mode: the mux mode for this pin.
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* @input_reg: the select input register offset for this pin if any
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* 0 if no select input setting needed.
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* @input_val: the select input value for this pin.
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* @configs: the config for this pin.
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*/
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struct imx_pin {
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unsigned int pin;
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unsigned int mux_mode;
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u16 input_reg;
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unsigned int input_val;
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unsigned long config;
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};
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/**
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* struct imx_pin_reg - describe a pin reg map
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* @mux_reg: mux register offset
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* @conf_reg: config register offset
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*/
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struct imx_pin_reg {
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s16 mux_reg;
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s16 conf_reg;
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};
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/* decode a generic config into raw register value */
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struct imx_cfg_params_decode {
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enum pin_config_param param;
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u32 mask;
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u8 shift;
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bool invert;
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};
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struct imx_pinctrl_soc_info {
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struct device *dev;
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const struct pinctrl_pin_desc *pins;
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unsigned int npins;
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struct imx_pin_reg *pin_regs;
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unsigned int group_index;
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unsigned int flags;
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const char *gpr_compatible;
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struct mutex mutex;
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/* generic pinconf */
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bool generic_pinconf;
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const struct pinconf_generic_params *custom_params;
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unsigned int num_custom_params;
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struct imx_cfg_params_decode *decodes;
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unsigned int num_decodes;
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void (*fixup)(unsigned long *configs, unsigned int num_configs,
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u32 *raw_config);
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};
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#define IMX_CFG_PARAMS_DECODE(p, m, o) \
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{ .param = p, .mask = m, .shift = o, .invert = false, }
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#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
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{ .param = p, .mask = m, .shift = o, .invert = true, }
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#define SHARE_MUX_CONF_REG 0x1
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#define ZERO_OFFSET_VALID 0x2
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#define NO_MUX 0x0
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#define NO_PAD 0x0
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#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
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#define PAD_CTL_MASK(len) ((1 << len) - 1)
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#define IMX_MUX_MASK 0x7
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#define IOMUXC_CONFIG_SION (0x1 << 4)
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int imx_pinctrl_probe(struct platform_device *pdev,
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struct imx_pinctrl_soc_info *info);
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#endif /* __DRIVERS_PINCTRL_IMX_H */
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