a5d4f3ad3a
Pass the register type to the prolog, also provides alternate "HV" version of hardware interrupt (0x500) and adjust LPES accordingly We tag those interrupts by setting bit 0x2 in the trap number Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
67 lines
1.4 KiB
ArmAsm
67 lines
1.4 KiB
ArmAsm
/*
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* This file contains low level CPU setup functions.
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/cache.h>
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/* Entry: r3 = crap, r4 = ptr to cputable entry
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*
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* Note that we can be called twice for pseudo-PVRs
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*/
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_GLOBAL(__setup_cpu_power7)
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mflr r11
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bl __init_hvmode_206
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mtlr r11
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beqlr
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bl __init_LPCR
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mtlr r11
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blr
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_GLOBAL(__restore_cpu_power7)
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mflr r11
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mfmsr r3
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rldicl. r0,r3,4,63
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beqlr
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bl __init_LPCR
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mtlr r11
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blr
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__init_hvmode_206:
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/* Disable CPU_FTR_HVMODE_206 and exit if MSR:HV is not set */
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mfmsr r3
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rldicl. r0,r3,4,63
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bnelr
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ld r5,CPU_SPEC_FEATURES(r4)
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LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE_206)
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xor r5,r5,r6
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std r5,CPU_SPEC_FEATURES(r4)
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blr
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__init_LPCR:
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/* Setup a sane LPCR:
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*
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* LPES = 0b01 (HSRR0/1 used for 0x500)
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* PECE = 0b111
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*
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* Other bits untouched for now
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*/
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mfspr r3,SPRN_LPCR
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ori r3,r3,(LPCR_LPES0|LPCR_LPES1)
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xori r3,r3, LPCR_LPES0
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ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
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mtspr SPRN_LPCR,r3
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isync
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blr
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