linux/arch
Rick Edgecombe a5f6c2ace9 x86/shstk: Add user control-protection fault handler
A control-protection fault is triggered when a control-flow transfer
attempt violates Shadow Stack or Indirect Branch Tracking constraints.
For example, the return address for a RET instruction differs from the copy
on the shadow stack.

There already exists a control-protection fault handler for handling kernel
IBT faults. Refactor this fault handler into separate user and kernel
handlers, like the page fault handler. Add a control-protection handler
for usermode. To avoid ifdeffery, put them both in a new file cet.c, which
is compiled in the case of either of the two CET features supported in the
kernel: kernel IBT or user mode shadow stack. Move some static inline
functions from traps.c into a header so they can be used in cet.c.

Opportunistically fix a comment in the kernel IBT part of the fault
handler that is on the end of the line instead of preceding it.

Keep the same behavior for the kernel side of the fault handler, except for
converting a BUG to a WARN in the case of a #CP happening when the feature
is missing. This unifies the behavior with the new shadow stack code, and
also prevents the kernel from crashing under this situation which is
potentially recoverable.

The control-protection fault handler works in a similar way as the general
protection fault handler. It provides the si_code SEGV_CPERR to the signal
handler.

Co-developed-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Yu-cheng Yu <yu-cheng.yu@intel.com>
Signed-off-by: Rick Edgecombe <rick.p.edgecombe@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Reviewed-by: Borislav Petkov (AMD) <bp@alien8.de>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mike Rapoport (IBM) <rppt@kernel.org>
Tested-by: Pengfei Xu <pengfei.xu@intel.com>
Tested-by: John Allen <john.allen@amd.com>
Tested-by: Kees Cook <keescook@chromium.org>
Link: https://lore.kernel.org/all/20230613001108.3040476-28-rick.p.edgecombe%40intel.com
2023-08-02 15:01:50 -07:00
..
alpha mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
arc mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
arm x86/shstk: Add user control-protection fault handler 2023-08-02 15:01:50 -07:00
arm64 x86/shstk: Add user control-protection fault handler 2023-08-02 15:01:50 -07:00
csky mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
hexagon mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
ia64 mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
loongarch mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
m68k mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
microblaze mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
mips mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
nios2 mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
openrisc mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
parisc mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
powerpc mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
riscv mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
s390 mm: Move pte/pmd_mkwrite() callers with no VMA to _novma() 2023-07-11 14:10:57 -07:00
sh mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
sparc x86/shstk: Add user control-protection fault handler 2023-08-02 15:01:50 -07:00
um mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
x86 x86/shstk: Add user control-protection fault handler 2023-08-02 15:01:50 -07:00
xtensa mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00
.gitignore
Kconfig mm: Rename arch pte_mkwrite()'s to pte_mkwrite_novma() 2023-07-11 14:10:56 -07:00