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linux/drivers/gpu/drm/amd/include/asic_reg/dcn
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Tom St Denis e49db37634 drm/amd/amdgpu: Add missing BASE_IDX to dcn register 
The register mmOTG1_OTG_BLANK_CONTROL was missing BASE_IDX value.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-03-05 15:11:32 -05:00
..
dcn_1_0_offset.h
drm/amd/include: Add HUBPREQ_DEBUG register offsets
2019-04-23 17:27:08 -05:00
dcn_1_0_sh_mask.h
drm/amdgpu: Add CM_TEST_DEBUG regs for DCN
2018-04-11 13:07:35 -05:00
dcn_2_0_0_offset.h
drm/amd/include: Add OCSC registers
2020-01-16 13:41:06 -05:00
dcn_2_0_0_sh_mask.h
drm/amd/include: Add OCSC registers
2020-01-16 13:41:06 -05:00
dcn_2_1_0_offset.h
drm/amd/include: Add OCSC registers
2020-01-16 13:41:06 -05:00
dcn_2_1_0_sh_mask.h
drm/amd/include: Add OCSC registers
2020-01-16 13:41:06 -05:00
dcn_3_0_0_offset.h
drm/amd/amdgpu: Add missing BASE_IDX to dcn register
2021-03-05 15:11:32 -05:00
dcn_3_0_0_sh_mask.h
drm/amd/display: remove unintended executable mode
2020-08-24 12:23:02 -04:00
dcn_3_0_1_offset.h
drm/amdgpu: add vangogh asic header files (v2)
2020-10-05 15:14:02 -04:00
dcn_3_0_1_sh_mask.h
drm/amdgpu: add vangogh asic header files (v2)
2020-10-05 15:14:02 -04:00
dcn_3_0_2_offset.h
drm/amdgpu: Add and use seperate reg headers for dcn302
2020-11-10 14:15:08 -05:00
dcn_3_0_2_sh_mask.h
drm/amdgpu: Add and use seperate reg headers for dcn302
2020-11-10 14:15:08 -05:00
dpcs_3_0_0_offset.h
drm/amd/display: remove unintended executable mode
2020-08-24 12:23:02 -04:00
dpcs_3_0_0_sh_mask.h
drm/amd/display: remove unintended executable mode
2020-08-24 12:23:02 -04:00