a6d268c619
Debugfs extension for Intel IOMMU to dump Interrupt remapping table entries for Interrupt remapping and Interrupt posting. The file /sys/kernel/debug/iommu/intel/ir_translation_struct provides detailed information, such as Index, Source Id, Destination Id, Vector and the IRTE values for entries with the present bit set, in the format shown. Remapped Interrupt supported on IOMMU: dmar1 IR table address:85e500000 Entry SrcID DstID Vct IRTE_high IRTE_low 24 01:00.0 00000001 24 0000000000040100 000000010024000d 25 01:00.0 00000004 22 0000000000040100 000000040022000d Posted Interrupt supported on IOMMU: dmar5 IR table address:85ec00000 Entry SrcID PDA_high PDA_low Vct IRTE_high IRTE_low 4 43:00.0 0000000f ff765980 41 0000000f00044300 ff76598000418001 5 43:00.0 0000000f ff765980 51 0000000f00044300 ff76598000518001 Cc: Lu Baolu <baolu.lu@linux.intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: Ashok Raj <ashok.raj@intel.com> Co-Developed-by: Gayatri Kammela <gayatri.kammela@intel.com> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Sohil Mehta <sohil.mehta@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
250 lines
6.8 KiB
C
250 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright © 2018 Intel Corporation.
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*
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* Authors: Gayatri Kammela <gayatri.kammela@intel.com>
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* Sohil Mehta <sohil.mehta@intel.com>
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* Jacob Pan <jacob.jun.pan@linux.intel.com>
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*/
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#include <linux/debugfs.h>
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#include <linux/dmar.h>
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#include <linux/intel-iommu.h>
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#include <linux/pci.h>
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#include <asm/irq_remapping.h>
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struct iommu_regset {
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int offset;
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const char *regs;
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};
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#define IOMMU_REGSET_ENTRY(_reg_) \
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{ DMAR_##_reg_##_REG, __stringify(_reg_) }
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static const struct iommu_regset iommu_regs[] = {
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IOMMU_REGSET_ENTRY(VER),
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IOMMU_REGSET_ENTRY(CAP),
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IOMMU_REGSET_ENTRY(ECAP),
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IOMMU_REGSET_ENTRY(GCMD),
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IOMMU_REGSET_ENTRY(GSTS),
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IOMMU_REGSET_ENTRY(RTADDR),
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IOMMU_REGSET_ENTRY(CCMD),
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IOMMU_REGSET_ENTRY(FSTS),
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IOMMU_REGSET_ENTRY(FECTL),
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IOMMU_REGSET_ENTRY(FEDATA),
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IOMMU_REGSET_ENTRY(FEADDR),
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IOMMU_REGSET_ENTRY(FEUADDR),
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IOMMU_REGSET_ENTRY(AFLOG),
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IOMMU_REGSET_ENTRY(PMEN),
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IOMMU_REGSET_ENTRY(PLMBASE),
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IOMMU_REGSET_ENTRY(PLMLIMIT),
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IOMMU_REGSET_ENTRY(PHMBASE),
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IOMMU_REGSET_ENTRY(PHMLIMIT),
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IOMMU_REGSET_ENTRY(IQH),
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IOMMU_REGSET_ENTRY(IQT),
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IOMMU_REGSET_ENTRY(IQA),
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IOMMU_REGSET_ENTRY(ICS),
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IOMMU_REGSET_ENTRY(IRTA),
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IOMMU_REGSET_ENTRY(PQH),
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IOMMU_REGSET_ENTRY(PQT),
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IOMMU_REGSET_ENTRY(PQA),
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IOMMU_REGSET_ENTRY(PRS),
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IOMMU_REGSET_ENTRY(PECTL),
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IOMMU_REGSET_ENTRY(PEDATA),
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IOMMU_REGSET_ENTRY(PEADDR),
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IOMMU_REGSET_ENTRY(PEUADDR),
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IOMMU_REGSET_ENTRY(MTRRCAP),
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IOMMU_REGSET_ENTRY(MTRRDEF),
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IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
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IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
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IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
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IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
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IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
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IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
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IOMMU_REGSET_ENTRY(VCCAP),
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IOMMU_REGSET_ENTRY(VCMD),
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IOMMU_REGSET_ENTRY(VCRSP),
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};
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static int iommu_regset_show(struct seq_file *m, void *unused)
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{
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu;
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unsigned long flag;
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int i, ret = 0;
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u64 value;
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rcu_read_lock();
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for_each_active_iommu(iommu, drhd) {
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if (!drhd->reg_base_addr) {
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seq_puts(m, "IOMMU: Invalid base address\n");
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ret = -EINVAL;
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goto out;
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}
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seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
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iommu->name, drhd->reg_base_addr);
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seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
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/*
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* Publish the contents of the 64-bit hardware registers
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* by adding the offset to the pointer (virtual address).
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*/
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raw_spin_lock_irqsave(&iommu->register_lock, flag);
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for (i = 0 ; i < ARRAY_SIZE(iommu_regs); i++) {
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value = dmar_readq(iommu->reg + iommu_regs[i].offset);
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seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
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iommu_regs[i].regs, iommu_regs[i].offset,
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value);
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}
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raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
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seq_putc(m, '\n');
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}
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out:
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rcu_read_unlock();
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return ret;
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}
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DEFINE_SHOW_ATTRIBUTE(iommu_regset);
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#ifdef CONFIG_IRQ_REMAP
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static void ir_tbl_remap_entry_show(struct seq_file *m,
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struct intel_iommu *iommu)
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{
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struct irte *ri_entry;
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unsigned long flags;
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int idx;
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seq_puts(m, " Entry SrcID DstID Vct IRTE_high\t\tIRTE_low\n");
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
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ri_entry = &iommu->ir_table->base[idx];
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if (!ri_entry->present || ri_entry->p_pst)
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continue;
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seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x %016llx\t%016llx\n",
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idx, PCI_BUS_NUM(ri_entry->sid),
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PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
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ri_entry->dest_id, ri_entry->vector,
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ri_entry->high, ri_entry->low);
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}
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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}
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static void ir_tbl_posted_entry_show(struct seq_file *m,
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struct intel_iommu *iommu)
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{
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struct irte *pi_entry;
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unsigned long flags;
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int idx;
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seq_puts(m, " Entry SrcID PDA_high PDA_low Vct IRTE_high\t\tIRTE_low\n");
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raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
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for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
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pi_entry = &iommu->ir_table->base[idx];
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if (!pi_entry->present || !pi_entry->p_pst)
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continue;
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seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x %016llx\t%016llx\n",
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idx, PCI_BUS_NUM(pi_entry->sid),
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PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
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pi_entry->pda_h, pi_entry->pda_l << 6,
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pi_entry->vector, pi_entry->high,
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pi_entry->low);
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}
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raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
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}
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/*
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* For active IOMMUs go through the Interrupt remapping
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* table and print valid entries in a table format for
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* Remapped and Posted Interrupts.
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*/
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static int ir_translation_struct_show(struct seq_file *m, void *unused)
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{
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struct dmar_drhd_unit *drhd;
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struct intel_iommu *iommu;
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u64 irta;
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rcu_read_lock();
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for_each_active_iommu(iommu, drhd) {
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if (!ecap_ir_support(iommu->ecap))
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continue;
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seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
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iommu->name);
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if (iommu->ir_table) {
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irta = virt_to_phys(iommu->ir_table->base);
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seq_printf(m, " IR table address:%llx\n", irta);
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ir_tbl_remap_entry_show(m, iommu);
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} else {
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seq_puts(m, "Interrupt Remapping is not enabled\n");
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}
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seq_putc(m, '\n');
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}
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seq_puts(m, "****\n\n");
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for_each_active_iommu(iommu, drhd) {
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if (!cap_pi_support(iommu->cap))
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continue;
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seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
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iommu->name);
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if (iommu->ir_table) {
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irta = virt_to_phys(iommu->ir_table->base);
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seq_printf(m, " IR table address:%llx\n", irta);
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ir_tbl_posted_entry_show(m, iommu);
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} else {
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seq_puts(m, "Interrupt Remapping is not enabled\n");
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}
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seq_putc(m, '\n');
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}
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rcu_read_unlock();
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
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#endif
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void __init intel_iommu_debugfs_init(void)
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{
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struct dentry *intel_iommu_debug = debugfs_create_dir("intel",
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iommu_debugfs_dir);
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debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
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&iommu_regset_fops);
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#ifdef CONFIG_IRQ_REMAP
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debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
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NULL, &ir_translation_struct_fops);
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#endif
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}
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