a6d70a878e
In Spectrum the key (and mask) block layout is very straight forward and every block is 16 bytes aligned. However, in Spectrum-2 the blocks are not even byte aligned, which makes it difficult to encode them using current method. Instead, first encode each block and then encode the block in the general blocks layout. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
249 lines
10 KiB
C
249 lines
10 KiB
C
/*
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* drivers/net/ethernet/mellanox/mlxsw/spectrum_acl_flex_keys.c
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* Copyright (c) 2017-2018 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2017-2018 Jiri Pirko <jiri@mellanox.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the names of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include "spectrum.h"
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#include "item.h"
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#include "core_acl_flex_keys.h"
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_dmac[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DMAC_32_47, 0x00, 2),
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MLXSW_AFK_ELEMENT_INST_BUF(DMAC_0_31, 0x02, 4),
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MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 13, 3),
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MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
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MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 8),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_smac[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SMAC_32_47, 0x00, 2),
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MLXSW_AFK_ELEMENT_INST_BUF(SMAC_0_31, 0x02, 4),
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MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 13, 3),
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MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
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MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 8),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l2_smac_ex[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SMAC_32_47, 0x02, 2),
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MLXSW_AFK_ELEMENT_INST_BUF(SMAC_0_31, 0x04, 4),
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MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x0C, 0, 16),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_sip[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
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MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 8),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_dip[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_0_31, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
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MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x0C, 0, 8),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_U32(IP_ECN, 0x04, 4, 2),
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MLXSW_AFK_ELEMENT_INST_U32(IP_TTL_, 0x04, 24, 8),
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MLXSW_AFK_ELEMENT_INST_U32(IP_DSCP, 0x08, 0, 6),
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MLXSW_AFK_ELEMENT_INST_U32(TCP_FLAGS, 0x08, 8, 9), /* TCP_CONTROL+TCP_ECN */
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_ex[] = {
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MLXSW_AFK_ELEMENT_INST_U32(VID, 0x00, 0, 12),
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MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x08, 29, 3),
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MLXSW_AFK_ELEMENT_INST_U32(SRC_L4_PORT, 0x08, 0, 16),
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MLXSW_AFK_ELEMENT_INST_U32(DST_L4_PORT, 0x0C, 0, 16),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_dip[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_32_63, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_0_31, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_ex1[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_96_127, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_64_95, 0x04, 4),
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MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x08, 0, 8),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_sip[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_32_63, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_sip_ex[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_96_127, 0x00, 4),
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_64_95, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_packet_type[] = {
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MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x00, 0, 16),
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};
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static const struct mlxsw_afk_block mlxsw_sp1_afk_blocks[] = {
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MLXSW_AFK_BLOCK(0x10, mlxsw_sp_afk_element_info_l2_dmac),
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MLXSW_AFK_BLOCK(0x11, mlxsw_sp_afk_element_info_l2_smac),
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MLXSW_AFK_BLOCK(0x12, mlxsw_sp_afk_element_info_l2_smac_ex),
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MLXSW_AFK_BLOCK(0x30, mlxsw_sp_afk_element_info_ipv4_sip),
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MLXSW_AFK_BLOCK(0x31, mlxsw_sp_afk_element_info_ipv4_dip),
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MLXSW_AFK_BLOCK(0x32, mlxsw_sp_afk_element_info_ipv4),
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MLXSW_AFK_BLOCK(0x33, mlxsw_sp_afk_element_info_ipv4_ex),
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MLXSW_AFK_BLOCK(0x60, mlxsw_sp_afk_element_info_ipv6_dip),
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MLXSW_AFK_BLOCK(0x65, mlxsw_sp_afk_element_info_ipv6_ex1),
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MLXSW_AFK_BLOCK(0x62, mlxsw_sp_afk_element_info_ipv6_sip),
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MLXSW_AFK_BLOCK(0x63, mlxsw_sp_afk_element_info_ipv6_sip_ex),
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MLXSW_AFK_BLOCK(0xB0, mlxsw_sp_afk_element_info_packet_type),
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};
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#define MLXSW_SP1_AFK_KEY_BLOCK_SIZE 16
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static void mlxsw_sp1_afk_encode_block(char *block, int block_index,
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char *output)
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{
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unsigned int offset = block_index * MLXSW_SP1_AFK_KEY_BLOCK_SIZE;
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char *output_indexed = output + offset;
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memcpy(output_indexed, block, MLXSW_SP1_AFK_KEY_BLOCK_SIZE);
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}
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const struct mlxsw_afk_ops mlxsw_sp1_afk_ops = {
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.blocks = mlxsw_sp1_afk_blocks,
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.blocks_count = ARRAY_SIZE(mlxsw_sp1_afk_blocks),
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.encode_block = mlxsw_sp1_afk_encode_block,
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_0[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DMAC_0_31, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_1[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SMAC_0_31, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_2[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SMAC_32_47, 0x04, 2),
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MLXSW_AFK_ELEMENT_INST_BUF(DMAC_32_47, 0x06, 2),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_3[] = {
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MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x00, 0, 3),
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MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
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MLXSW_AFK_ELEMENT_INST_BUF(DMAC_32_47, 0x06, 2),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_4[] = {
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MLXSW_AFK_ELEMENT_INST_U32(PCP, 0x00, 0, 3),
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MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
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MLXSW_AFK_ELEMENT_INST_U32(ETHERTYPE, 0x04, 0, 16),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_mac_5[] = {
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MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
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MLXSW_AFK_ELEMENT_INST_U32(SRC_SYS_PORT, 0x04, 0, 8), /* RX_ACL_SYSTEM_PORT */
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_0[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_0_31, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_1[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_0_31, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv4_2[] = {
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MLXSW_AFK_ELEMENT_INST_U32(IP_DSCP, 0x04, 0, 6),
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MLXSW_AFK_ELEMENT_INST_U32(IP_ECN, 0x04, 6, 2),
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MLXSW_AFK_ELEMENT_INST_U32(IP_TTL_, 0x04, 8, 8),
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MLXSW_AFK_ELEMENT_INST_U32(IP_PROTO, 0x04, 16, 8),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_0[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_32_63, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_1[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_64_95, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_2[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(DST_IP_96_127, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_3[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_32_63, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_4[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_64_95, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_ipv6_5[] = {
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MLXSW_AFK_ELEMENT_INST_BUF(SRC_IP_96_127, 0x04, 4),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l4_0[] = {
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MLXSW_AFK_ELEMENT_INST_U32(SRC_L4_PORT, 0x04, 16, 16),
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MLXSW_AFK_ELEMENT_INST_U32(DST_L4_PORT, 0x04, 0, 16),
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};
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static struct mlxsw_afk_element_inst mlxsw_sp_afk_element_info_l4_2[] = {
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MLXSW_AFK_ELEMENT_INST_U32(TCP_FLAGS, 0x04, 16, 9), /* TCP_CONTROL + TCP_ECN */
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};
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static const struct mlxsw_afk_block mlxsw_sp2_afk_blocks[] = {
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MLXSW_AFK_BLOCK(0x10, mlxsw_sp_afk_element_info_mac_0),
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MLXSW_AFK_BLOCK(0x11, mlxsw_sp_afk_element_info_mac_1),
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MLXSW_AFK_BLOCK(0x12, mlxsw_sp_afk_element_info_mac_2),
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MLXSW_AFK_BLOCK(0x13, mlxsw_sp_afk_element_info_mac_3),
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MLXSW_AFK_BLOCK(0x14, mlxsw_sp_afk_element_info_mac_4),
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MLXSW_AFK_BLOCK(0x15, mlxsw_sp_afk_element_info_mac_5),
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MLXSW_AFK_BLOCK(0x38, mlxsw_sp_afk_element_info_ipv4_0),
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MLXSW_AFK_BLOCK(0x39, mlxsw_sp_afk_element_info_ipv4_1),
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MLXSW_AFK_BLOCK(0x3A, mlxsw_sp_afk_element_info_ipv4_2),
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MLXSW_AFK_BLOCK(0x40, mlxsw_sp_afk_element_info_ipv6_0),
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MLXSW_AFK_BLOCK(0x41, mlxsw_sp_afk_element_info_ipv6_1),
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MLXSW_AFK_BLOCK(0x42, mlxsw_sp_afk_element_info_ipv6_2),
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MLXSW_AFK_BLOCK(0x43, mlxsw_sp_afk_element_info_ipv6_3),
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MLXSW_AFK_BLOCK(0x44, mlxsw_sp_afk_element_info_ipv6_4),
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MLXSW_AFK_BLOCK(0x45, mlxsw_sp_afk_element_info_ipv6_5),
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MLXSW_AFK_BLOCK(0x90, mlxsw_sp_afk_element_info_l4_0),
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MLXSW_AFK_BLOCK(0x92, mlxsw_sp_afk_element_info_l4_2),
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};
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const struct mlxsw_afk_ops mlxsw_sp2_afk_ops = {
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.blocks = mlxsw_sp2_afk_blocks,
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.blocks_count = ARRAY_SIZE(mlxsw_sp2_afk_blocks),
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};
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