110a2432c5
Aquantia PHY's of the AQR107 family support the downshift feature. Add support for it as standard PHY tunable so that it can be controlled via ethtool. The AQCS109 supports a proprietary 2-pair 1Gbps mode. If two such PHY's are connected to each other with a 2-pair cable, they may not be able to establish a link if both advertise modes > 1Gbps. v2: - add downshift event detection - warn if downshift occurred - read downshifted rate from vendor register - enable downshift per default on all AQR107 family members Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
478 lines
13 KiB
C
478 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Aquantia PHY
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*
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* Author: Shaohui Xie <Shaohui.Xie@freescale.com>
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*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/bitfield.h>
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#include <linux/phy.h>
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#include "aquantia.h"
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#define PHY_ID_AQ1202 0x03a1b445
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#define PHY_ID_AQ2104 0x03a1b460
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#define PHY_ID_AQR105 0x03a1b4a2
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#define PHY_ID_AQR106 0x03a1b4d0
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#define PHY_ID_AQR107 0x03a1b4e0
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#define PHY_ID_AQCS109 0x03a1b5c2
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#define PHY_ID_AQR405 0x03a1b4b0
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#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
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#define MDIO_AN_VEND_PROV 0xc400
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#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
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#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
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#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
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#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
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#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
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#define MDIO_AN_TX_VEND_STATUS1 0xc800
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#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
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#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
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#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
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#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
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#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
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#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
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#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
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#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
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#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
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#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
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#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
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#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
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#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
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#define MDIO_AN_RX_LP_STAT1 0xe820
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#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
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#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
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/* Vendor specific 1, MDIO_MMD_VEND1 */
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#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
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#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
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#define VEND1_GLOBAL_INT_STD_MASK 0xff00
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#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
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#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
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#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
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#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
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#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
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#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
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#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
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#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
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#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
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#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
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#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
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#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
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#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
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#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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static int aqr_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u16 reg;
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int ret;
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if (phydev->autoneg == AUTONEG_DISABLE)
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return genphy_c45_pma_setup_forced(phydev);
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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/* Clause 45 has no standardized support for 1000BaseT, therefore
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* use vendor registers for this mode.
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*/
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reg = 0;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->advertising))
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reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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phydev->advertising))
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reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
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MDIO_AN_VEND_PROV_1000BASET_HALF |
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MDIO_AN_VEND_PROV_1000BASET_FULL, reg);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int aqr_config_intr(struct phy_device *phydev)
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{
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int err;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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err = phy_write_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_MASK2,
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MDIO_AN_TX_VEND_INT_MASK2_LINK);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_STD_MASK,
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VEND1_GLOBAL_INT_STD_MASK_ALL);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_VEND_MASK,
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VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
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VEND1_GLOBAL_INT_VEND_MASK_AN);
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} else {
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err = phy_write_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_MASK2, 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_STD_MASK, 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_INT_VEND_MASK, 0);
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}
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return err;
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}
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static int aqr_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_STATUS2);
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return (reg < 0) ? reg : 0;
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}
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static int aqr_read_status(struct phy_device *phydev)
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{
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int val;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->lp_advertising,
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val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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phydev->lp_advertising,
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val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
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}
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return genphy_c45_read_status(phydev);
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}
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static int aqr107_read_downshift_event(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS1);
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if (val < 0)
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return val;
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return !!(val & MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT);
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}
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static int aqr107_read_rate(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
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if (val < 0)
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return val;
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switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
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case MDIO_AN_TX_VEND_STATUS1_10BASET:
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phydev->speed = SPEED_10;
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break;
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case MDIO_AN_TX_VEND_STATUS1_100BASETX:
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phydev->speed = SPEED_100;
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break;
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case MDIO_AN_TX_VEND_STATUS1_1000BASET:
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phydev->speed = SPEED_1000;
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break;
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case MDIO_AN_TX_VEND_STATUS1_2500BASET:
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phydev->speed = SPEED_2500;
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break;
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case MDIO_AN_TX_VEND_STATUS1_5000BASET:
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phydev->speed = SPEED_5000;
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break;
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case MDIO_AN_TX_VEND_STATUS1_10GBASET:
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phydev->speed = SPEED_10000;
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break;
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default:
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phydev->speed = SPEED_UNKNOWN;
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break;
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}
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if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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return 0;
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}
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static int aqr107_read_status(struct phy_device *phydev)
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{
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int val, ret;
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ret = aqr_read_status(phydev);
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if (ret)
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return ret;
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if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
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return 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
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if (val < 0)
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return val;
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switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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break;
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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break;
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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break;
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default:
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phydev->interface = PHY_INTERFACE_MODE_NA;
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break;
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}
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val = aqr107_read_downshift_event(phydev);
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if (val <= 0)
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return val;
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phydev_warn(phydev, "Downshift occurred! Cabling may be defective.\n");
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/* Read downshifted rate from vendor register */
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return aqr107_read_rate(phydev);
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}
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static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
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{
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int val, cnt, enable;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
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if (val < 0)
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return val;
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enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
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cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
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*data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
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return 0;
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}
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static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
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{
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int val = 0;
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if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
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return -E2BIG;
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if (cnt != DOWNSHIFT_DEV_DISABLE) {
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val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
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val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
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}
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return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
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MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
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MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
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}
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static int aqr107_get_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return aqr107_get_downshift(phydev, data);
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default:
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return -EOPNOTSUPP;
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}
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}
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static int aqr107_set_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, const void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return aqr107_set_downshift(phydev, *(const u8 *)data);
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default:
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return -EOPNOTSUPP;
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}
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}
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static int aqr107_config_init(struct phy_device *phydev)
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{
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/* Check that the PHY interface type is compatible */
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
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phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
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phydev->interface != PHY_INTERFACE_MODE_10GKR)
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return -ENODEV;
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/* ensure that a latched downshift event is cleared */
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aqr107_read_downshift_event(phydev);
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return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
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}
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static int aqcs109_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Check that the PHY interface type is compatible */
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if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
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phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
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return -ENODEV;
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/* AQCS109 belongs to a chip family partially supporting 10G and 5G.
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* PMA speed ability bits are the same for all members of the family,
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* AQCS109 however supports speeds up to 2.5G only.
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*/
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ret = phy_set_max_speed(phydev, SPEED_2500);
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if (ret)
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return ret;
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/* ensure that a latched downshift event is cleared */
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aqr107_read_downshift_event(phydev);
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return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
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}
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static struct phy_driver aqr_driver[] = {
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
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.name = "Aquantia AQ1202",
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.aneg_done = genphy_c45_aneg_done,
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.get_features = genphy_c45_pma_read_abilities,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
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.name = "Aquantia AQ2104",
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.aneg_done = genphy_c45_aneg_done,
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.get_features = genphy_c45_pma_read_abilities,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
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.name = "Aquantia AQR105",
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.aneg_done = genphy_c45_aneg_done,
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.get_features = genphy_c45_pma_read_abilities,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
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.name = "Aquantia AQR106",
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.aneg_done = genphy_c45_aneg_done,
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.get_features = genphy_c45_pma_read_abilities,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr_read_status,
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},
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{
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PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
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.name = "Aquantia AQR107",
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.aneg_done = genphy_c45_aneg_done,
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.get_features = genphy_c45_pma_read_abilities,
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.probe = aqr_hwmon_probe,
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.config_init = aqr107_config_init,
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.config_aneg = aqr_config_aneg,
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.config_intr = aqr_config_intr,
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.ack_interrupt = aqr_ack_interrupt,
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.read_status = aqr107_read_status,
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.get_tunable = aqr107_get_tunable,
|
|
.set_tunable = aqr107_set_tunable,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
|
|
.name = "Aquantia AQCS109",
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.probe = aqr_hwmon_probe,
|
|
.config_init = aqcs109_config_init,
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr107_read_status,
|
|
.get_tunable = aqr107_get_tunable,
|
|
.set_tunable = aqr107_set_tunable,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
|
|
.name = "Aquantia AQR405",
|
|
.aneg_done = genphy_c45_aneg_done,
|
|
.get_features = genphy_c45_pma_read_abilities,
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr_read_status,
|
|
},
|
|
};
|
|
|
|
module_phy_driver(aqr_driver);
|
|
|
|
static struct mdio_device_id __maybe_unused aqr_tbl[] = {
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, aqr_tbl);
|
|
|
|
MODULE_DESCRIPTION("Aquantia PHY driver");
|
|
MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
|
|
MODULE_LICENSE("GPL v2");
|