Evan Quan a7e660e526 drm/amd/pm: expose the firmware_capability from firmware_info table ...

That will help to determine whether 2ND_USB20_PORT workaround is
needed for Sienna Cichlid.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2020-12-10 16:41:49 -05:00

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vega12

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amd_powerplay.h

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amdgpu_dpm.h

drm/amd/powerplay: add one sysfs file to support the feature to modify gfx clock on Raven/Raven2/Picasso APU.

2020-09-29 16:12:16 -04:00

amdgpu_pm.h

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amdgpu_smu.h

drm/amd/pm: expose the firmware_capability from firmware_info table

2020-12-10 16:41:49 -05:00

arcturus_ppsmc.h

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cz_ppsmc.h

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fiji_ppsmc.h

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hardwaremanager.h

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hwmgr.h

drm/amd/pm/powerplay/hwmgr/hwmgr: Move 'vega20_hwmgr_init()'s prototype to shared header

2020-12-01 16:04:45 -05:00

polaris10_pwrvirus.h

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power_state.h

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pp_debug.h

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pp_endian.h

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pp_thermal.h

drm/amd/pm/inc/pp_thermal: Mark 'SMU7Thermal{WithDelay}Policy' as __maybe_unused

2020-12-01 16:04:44 -05:00

ppinterrupt.h

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rv_ppsmc.h

drm/amdgpu: add amdgpu_gfx_state_change_set() set gfx power change entry (v2)

2020-11-13 17:29:45 -05:00

smu7_common.h

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smu7_discrete.h

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smu7_fusion.h

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smu7_ppsmc.h

drm/amd/pm: correct Polaris DIDT configurations

2020-10-27 11:59:16 -04:00

smu7.h

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smu8_fusion.h

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smu8.h

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smu9_driver_if.h

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smu9.h

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smu10_driver_if.h

drm/amd/pm: add Raven2 watermark WmType setting

2020-09-17 17:48:18 -04:00

smu10.h

drm/amd/pm: update smu10.h WORKLOAD_PPLIB setting for raven

2020-12-08 23:06:15 -05:00

smu11_driver_if_arcturus.h

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smu11_driver_if_navi10.h

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smu11_driver_if_sienna_cichlid.h

drm/amd/pm: update driver if file for sienna cichlid

2020-11-16 12:18:10 -05:00

smu11_driver_if_vangogh.h

drm/amd/pm: update the swSMU headers for vangogh

2020-11-13 00:12:51 -05:00

smu11_driver_if.h

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smu12_driver_if.h

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smu71_discrete.h

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smu71.h

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smu72_discrete.h

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smu72.h

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smu73_discrete.h

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smu73.h

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smu74_discrete.h

drm/amd/pm: correct VR shared rail info

2020-10-27 11:58:57 -04:00

smu74.h

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smu75_discrete.h

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smu75.h

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smu_11_0_cdr_table.h

drm/amd/pm: implement a new umc cdr workaround

2020-09-17 17:46:40 -04:00

smu_types.h

drm/amd/pm: correct the gpo control for sienna cichlid

2020-12-10 16:41:49 -05:00

smu_ucode_xfer_cz.h

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smu_ucode_xfer_vi.h

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smu_v11_0_7_ppsmc.h

drm/amd/pm: correct the gpo control for sienna cichlid

2020-12-10 16:41:49 -05:00

smu_v11_0_7_pptable.h

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smu_v11_0_ppsmc.h

drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares(V2)

2020-09-17 17:46:47 -04:00

smu_v11_0_pptable.h

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smu_v11_0.h

drm/amd/pm: update driver if version for dimgrey_cavefish

2020-12-08 23:05:21 -05:00

smu_v11_5_pmfw.h

drm/amd/pm: update the swSMU headers for vangogh

2020-11-13 00:12:51 -05:00

smu_v11_5_ppsmc.h

drm/amd/pm: update the swSMU headers for vangogh

2020-11-13 00:12:51 -05:00

smu_v12_0_ppsmc.h

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smu_v12_0.h

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smumgr.h

drm/amd/pm: perform SMC reset on suspend/hibernation

2020-10-30 01:00:43 -04:00

tonga_ppsmc.h

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vega10_ppsmc.h

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vega12_ppsmc.h

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vega20_ppsmc.h

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