7187bb7d0b
Cortex-X4 and Neoverse-V3 suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. This is described in their Software Developer Errata Notice (SDEN) documents: * Cortex-X4 SDEN v8.0, erratum 3194386: https://developer.arm.com/documentation/SDEN-2432808/0800/ * Neoverse-V3 SDEN v6.0, erratum 3312417: https://developer.arm.com/documentation/SDEN-2891958/0600/ To workaround these errata, it is necessary to place a speculation barrier (SB) after MSR to the SSBS special-purpose register. This patch adds the requisite SB after writes to SSBS within the kernel, and hides the presence of SSBS from EL0 such that userspace software which cares about SSBS will manipulate this via prctl(PR_GET_SPECULATION_CTRL, ...). Signed-off-by: Mark Rutland <mark.rutland@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20240508081400.235362-5-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org>
107 lines
1.8 KiB
Plaintext
107 lines
1.8 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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#
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# Internal CPU capabilities constants, keep this list sorted
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ALWAYS_BOOT
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ALWAYS_SYSTEM
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BTI
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# Unreliable: use system_supports_32bit_el0() instead.
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HAS_32BIT_EL0_DO_NOT_USE
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HAS_32BIT_EL1
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HAS_ADDRESS_AUTH
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HAS_ADDRESS_AUTH_ARCH_QARMA3
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HAS_ADDRESS_AUTH_ARCH_QARMA5
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HAS_ADDRESS_AUTH_IMP_DEF
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HAS_AMU_EXTN
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HAS_ARMv8_4_TTL
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HAS_CACHE_DIC
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HAS_CACHE_IDC
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HAS_CNP
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HAS_CRC32
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HAS_DCPODP
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HAS_DCPOP
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HAS_DIT
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HAS_E0PD
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HAS_ECV
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HAS_ECV_CNTPOFF
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HAS_EPAN
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HAS_EVT
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HAS_FPMR
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HAS_FGT
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HAS_FPSIMD
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HAS_GENERIC_AUTH
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HAS_GENERIC_AUTH_ARCH_QARMA3
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HAS_GENERIC_AUTH_ARCH_QARMA5
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HAS_GENERIC_AUTH_IMP_DEF
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HAS_GIC_CPUIF_SYSREGS
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HAS_GIC_PRIO_MASKING
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HAS_GIC_PRIO_RELAXED_SYNC
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HAS_HCR_NV1
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HAS_HCX
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HAS_LDAPR
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HAS_LPA2
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HAS_LSE_ATOMICS
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HAS_MOPS
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HAS_NESTED_VIRT
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HAS_PAN
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HAS_S1PIE
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HAS_RAS_EXTN
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HAS_RNG
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HAS_SB
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HAS_STAGE2_FWB
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HAS_TCR2
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HAS_TIDCP1
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HAS_TLB_RANGE
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HAS_VA52
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HAS_VIRT_HOST_EXTN
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HAS_WFXT
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HW_DBM
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KVM_HVHE
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KVM_PROTECTED_MODE
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MISMATCHED_CACHE_TYPE
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MTE
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MTE_ASYMM
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SME
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SME_FA64
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SME2
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SPECTRE_V2
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SPECTRE_V3A
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SPECTRE_V4
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SPECTRE_BHB
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SSBS
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SVE
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UNMAP_KERNEL_AT_EL0
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WORKAROUND_834220
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WORKAROUND_843419
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WORKAROUND_845719
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WORKAROUND_858921
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WORKAROUND_1418040
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WORKAROUND_1463225
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WORKAROUND_1508412
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WORKAROUND_1542419
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WORKAROUND_1742098
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WORKAROUND_1902691
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WORKAROUND_2038923
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WORKAROUND_2064142
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WORKAROUND_2077057
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WORKAROUND_2457168
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WORKAROUND_2645198
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WORKAROUND_2658417
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WORKAROUND_AMPERE_AC03_CPU_38
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WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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WORKAROUND_TSB_FLUSH_FAILURE
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WORKAROUND_TRBE_WRITE_OUT_OF_RANGE
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WORKAROUND_CAVIUM_23154
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WORKAROUND_CAVIUM_27456
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WORKAROUND_CAVIUM_30115
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WORKAROUND_CAVIUM_TX2_219_PRFM
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WORKAROUND_CAVIUM_TX2_219_TVM
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WORKAROUND_CLEAN_CACHE
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WORKAROUND_DEVICE_LOAD_ACQUIRE
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WORKAROUND_NVIDIA_CARMEL_CNP
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WORKAROUND_QCOM_FALKOR_E1003
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WORKAROUND_REPEAT_TLBI
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WORKAROUND_SPECULATIVE_AT
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WORKAROUND_SPECULATIVE_SSBS
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WORKAROUND_SPECULATIVE_UNPRIV_LOAD
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