linux

iv/linux

History

Palmer Dabbelt a8914b6cb8 Microchip RISC-V devicetrees for 5.20

A pair of changes for mpfs.dtsi:
 - A pair of patches from Suresh & I, removing the bogus max frequency
   properties from the controller nodes for {q,}spi. This is a device
   only property with no meaning for a controller and should never have
   been there.
 - RISC-V has no sensible defaults for cpu topology, so I added a this
   information to the dt for MPFS as a cpu-map. This is an optional
   property and therefore is not a fix.
 -----BEGIN PGP SIGNATURE-----
 
 iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCYtA5+QAKCRB4tDGHoIJi
 0mxQAQClNl7aSXot+veMiDqqEEoANPdatHbhUzn3F8Sx7sf2PAD9HoBz1elu726I
 kjEGugtcwpBaJ5xPnlhFxX3I6ffCMA8=
 =V++E
 -----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmLQjR8THHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRAuExnzX7sYiZC9D/9BVCL75FEL4qJoOJw1L8BAmZCisLr/
 OaKY+gg3hG/cT1EtHna+jx9w3kfHtaLVoB3CMwRns7s6TxT0tvDz3fiSBhLEFWzM
 n42b2l8jg89sAJEFBKuSoDU6w1h6y2mh++HhZ/vs82vcnFX7jceCAZQ6QX4kE3v1
 IzxL6SDGMOq6uqcjd7Pui8rcManLMT5vazCDzMlkVYLcjslwleorxXV42EhXDvi/
 yDobOnaJiBcp4wRxYUYVErAVLhqaCpPezdZIF/1s4OYjxn1t7btY6wmbbBhwyyDu
 w/bvUN7WcLqLqb0dNwQY5a1cpNxFWmGPWPFuzO3q68+YJz6OZqLqgJVUS2s+9Xd5
 h8HyMyXMJCBXwSYj1JEiSZl2o4J+Obeq1JnCkd1e4jw46H3ZiKvzJ3hFSDn9khrN
 0J5bYUSYzvYXCkzhcqr9e98MdD8BF8l0MNkczopQw6r7n6DrDCseG4DWHGlVHzMR
 5haQ13Mn9vH18nbD5j3vrpRFxsR1T72Tl7CNzoOdZFGu+29pgLVyGuhJblq0LEXT
 lBTcysueaxIEnll705UnaVy16aeOZi3E4Dm7NDqntyQbuHTA10aopmy6aoXbZ5Y6
 1Dw1rYPQuhRhzikmjCJ9gyK9urKaLzaGIKhL3WtY4HnpZDk6hq6gM2JihhPD2Y6K
 WYRn3VvkN7B2hw==
 =zank
 -----END PGP SIGNATURE-----

Merge tag 'dt-for-palmer-v5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git into for-next

Microchip RISC-V devicetrees for 5.20

A pair of changes for mpfs.dtsi:
- A pair of patches from Suresh & I, removing the bogus max frequency
  properties from the controller nodes for {q,}spi. This is a device
  only property with no meaning for a controller and should never have
  been there.
- RISC-V has no sensible defaults for cpu topology, so I added a this
  information to the dt for MPFS as a cpu-map. This is an optional
  property and therefore is not a fix.

* tag 'dt-for-palmer-v5.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git:
  riscv: dts: microchip: Add mpfs' topology information
  riscv: dts: microchip: remove spi-max-frequency property
  riscv: dts: microchip: remove spi-max-frequency property

2022-07-14 14:39:27 -07:00

boot

riscv: dts: microchip: Add mpfs' topology information

2022-07-07 23:15:39 +01:00

configs

RISC-V: Add CONFIG_{NON,}PORTABLE

2022-07-14 11:19:49 -07:00

errata

riscv: remove usage of function-pointers from cpufeatures and t-head errata

2022-06-16 15:47:41 -07:00

include

RISC-V: PCI: Avoid handing out address 0 to devices