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Correct timing's fp/sync/bp value based on the information below.
It should be noticed that the calculation formula should be changed
per sync polarity.
The sequence of signal: sync - backporch - video data - frontporch
The following registers start counting from sync's rising edge:
1. VR090: frame edge's left and right
2. VR094: frame edge's top and bottom
3. VR09C: counting from sync's rising edge to falling edge
[Vertical timing]
+--+ +-------------------+ +--+
| | | v i d e o | | |
+--+ +-----+ +-----+ +---+
vsync+--+
frame_top+--------+
frame_bottom+----------------------------+
+-------------------+
| v i d e o |
+--+ +-----+ +-----+ +---+
| | | |
+--+ +--+
vsync+-------------------------------+
frame_top+-----+
frame_bottom+-------------------------+
[Horizontal timing]
+--+ +-------------------+ +--+
| | | v i d e o | | |
+--+ +-----+ +-----+ +---+
hsync+--+
frame_left+--------+
frame_right+----------------------------+
+-------------------+
| v i d e o |
+--+ +-----+ +-----+ +---+
| | | |
+--+ +--+
hsync+-------------------------------+
frame_left+-----+
frame_right+-------------------------+
Ex. 1920x1200@60 whose vsync polarity is negative
VR098: c4d3efff, VR09C: 04cc001f
v-total = 0x4D3 (VR098[27:16]) = 1235
v-sync = 0x4CC (VR09C[27:16]) = 1228
[hverkuil: drop unused variable mds]
Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
a922a0cb05