fe811e1de3
Add the remaining bit locations for the module stop clock registers. Signed-off-by: Chris Brandt <chris.brandt@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
/*
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* Copyright (C) 2014 Renesas Solutions Corp.
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* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R7S72100_H__
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#define __DT_BINDINGS_CLOCK_R7S72100_H__
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#define R7S72100_CLK_PLL 0
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/* MSTP2 */
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#define R7S72100_CLK_CORESIGHT 0
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/* MSTP3 */
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#define R7S72100_CLK_IEBUS 7
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#define R7S72100_CLK_IRDA 6
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#define R7S72100_CLK_LIN0 5
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#define R7S72100_CLK_LIN1 4
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#define R7S72100_CLK_MTU2 3
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#define R7S72100_CLK_CAN 2
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#define R7S72100_CLK_ADCPWR 1
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#define R7S72100_CLK_PWM 0
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/* MSTP4 */
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#define R7S72100_CLK_SCIF0 7
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#define R7S72100_CLK_SCIF1 6
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#define R7S72100_CLK_SCIF2 5
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#define R7S72100_CLK_SCIF3 4
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#define R7S72100_CLK_SCIF4 3
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#define R7S72100_CLK_SCIF5 2
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#define R7S72100_CLK_SCIF6 1
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#define R7S72100_CLK_SCIF7 0
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/* MSTP5 */
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#define R7S72100_CLK_SCI0 7
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#define R7S72100_CLK_SCI1 6
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#define R7S72100_CLK_SG0 5
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#define R7S72100_CLK_SG1 4
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#define R7S72100_CLK_SG2 3
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#define R7S72100_CLK_SG3 2
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#define R7S72100_CLK_OSTM0 1
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#define R7S72100_CLK_OSTM1 0
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/* MSTP6 */
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#define R7S72100_CLK_ADC 7
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#define R7S72100_CLK_CEU 6
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#define R7S72100_CLK_DOC0 5
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#define R7S72100_CLK_DOC1 4
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#define R7S72100_CLK_DRC0 3
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#define R7S72100_CLK_DRC1 2
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#define R7S72100_CLK_JCU 1
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#define R7S72100_CLK_RTC 0
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/* MSTP7 */
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#define R7S72100_CLK_VDEC0 7
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#define R7S72100_CLK_VDEC1 6
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#define R7S72100_CLK_ETHER 4
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#define R7S72100_CLK_NAND 3
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#define R7S72100_CLK_USB0 1
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#define R7S72100_CLK_USB1 0
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/* MSTP8 */
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#define R7S72100_CLK_IMR0 7
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#define R7S72100_CLK_IMR1 6
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#define R7S72100_CLK_IMRDISP 5
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#define R7S72100_CLK_MMCIF 4
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#define R7S72100_CLK_MLB 3
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#define R7S72100_CLK_ETHAVB 2
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#define R7S72100_CLK_SCUX 1
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/* MSTP9 */
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#define R7S72100_CLK_I2C0 7
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#define R7S72100_CLK_I2C1 6
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#define R7S72100_CLK_I2C2 5
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#define R7S72100_CLK_I2C3 4
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#define R7S72100_CLK_SPIBSC0 3
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#define R7S72100_CLK_SPIBSC1 2
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#define R7S72100_CLK_VDC50 1 /* and LVDS */
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#define R7S72100_CLK_VDC51 0
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/* MSTP10 */
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#define R7S72100_CLK_SPI0 7
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#define R7S72100_CLK_SPI1 6
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#define R7S72100_CLK_SPI2 5
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#define R7S72100_CLK_SPI3 4
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#define R7S72100_CLK_SPI4 3
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#define R7S72100_CLK_CDROM 2
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#define R7S72100_CLK_SPDIF 1
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#define R7S72100_CLK_RGPVG2 0
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/* MSTP11 */
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#define R7S72100_CLK_SSI0 5
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#define R7S72100_CLK_SSI1 4
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#define R7S72100_CLK_SSI2 3
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#define R7S72100_CLK_SSI3 2
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#define R7S72100_CLK_SSI4 1
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#define R7S72100_CLK_SSI5 0
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/* MSTP12 */
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#define R7S72100_CLK_SDHI00 3
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#define R7S72100_CLK_SDHI01 2
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#define R7S72100_CLK_SDHI10 1
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#define R7S72100_CLK_SDHI11 0
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/* MSTP13 */
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#define R7S72100_CLK_PIX1 2
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#define R7S72100_CLK_PIX0 1
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#endif /* __DT_BINDINGS_CLOCK_R7S72100_H__ */
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