ca5b901c18
TI's J721E uses the Cadence CSI2RX and DPHY peripherals to facilitate capture over a CSI-2 bus. The TI CSI2RX platform driver glues all the parts together. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Tested-by: Julien Massot <julien.massot@collabora.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Jai Luthra <j-luthra@ti.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
101 lines
2.3 KiB
YAML
101 lines
2.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/ti,j721e-csi2rx-shim.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI J721E CSI2RX Shim
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description: |
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The TI J721E CSI2RX Shim is a wrapper around Cadence CSI2RX bridge that
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enables sending captured frames to memory over PSI-L DMA. In the J721E
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Technical Reference Manual (SPRUIL1B) it is referred to as "SHIM" under the
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CSI_RX_IF section.
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maintainers:
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- Jai Luthra <j-luthra@ti.com>
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properties:
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compatible:
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const: ti,j721e-csi2rx-shim
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dmas:
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maxItems: 1
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dma-names:
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items:
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- const: rx0
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reg:
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maxItems: 1
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power-domains:
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maxItems: 1
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ranges: true
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"#address-cells": true
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"#size-cells": true
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patternProperties:
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"^csi-bridge@":
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type: object
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description: CSI2 bridge node.
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$ref: cdns,csi2rx.yaml#
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required:
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- compatible
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- reg
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- dmas
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- dma-names
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- power-domains
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- ranges
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- "#address-cells"
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- "#size-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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ti_csi2rx0: ticsi2rx@4500000 {
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compatible = "ti,j721e-csi2rx-shim";
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dmas = <&main_udmap 0x4940>;
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dma-names = "rx0";
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reg = <0x4500000 0x1000>;
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power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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cdns_csi2rx: csi-bridge@4504000 {
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compatible = "ti,j721e-csi2rx", "cdns,csi2rx";
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reg = <0x4504000 0x1000>;
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clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
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<&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>;
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clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
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"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
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phys = <&dphy0>;
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phy-names = "dphy";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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csi2_0: port@0 {
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reg = <0>;
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csi2rx0_in_sensor: endpoint {
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remote-endpoint = <&csi2_cam0>;
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bus-type = <4>; /* CSI2 DPHY. */
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clock-lanes = <0>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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};
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