4053b6b43f
A common mistake when writing a device tree for a platform that is using GICv3 with ancient CPUs is to overlook the MMIO frames that implement the GICv2 compatibility feature, because this feature is implemented by the CPUs and not by the GIC itself. The compatibility feature itself is optional (all the modern implementations have dropped it), but is present in all the ARM Ltd implementations of the ARMv8.0 architecture (A3x, A53, A57, A72, A73), and many others from various implementers. Make it explicit that GICC, GICH and GICV are required for these CPUs. Also take this opportunity to update my email address, as people keep sending them to the wrong place... Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Krzysztof Kozlowski <krzk+dt@kernel.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220409101617.268796-1-maz@kernel.org
298 lines
8.2 KiB
YAML
298 lines
8.2 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM Generic Interrupt Controller, version 3
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maintainers:
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- Marc Zyngier <maz@kernel.org>
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description: |
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AArch64 SMP cores are often associated with a GICv3, providing Private
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Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
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Software Generated Interrupts (SGI), and Locality-specific Peripheral
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Interrupts (LPI).
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- qcom,msm8996-gic-v3
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- const: arm,gic-v3
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- const: arm,gic-v3
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interrupt-controller: true
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"#address-cells":
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enum: [ 0, 1, 2 ]
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"#size-cells":
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enum: [ 1, 2 ]
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ranges: true
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"#interrupt-cells":
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description: |
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Specifies the number of cells needed to encode an interrupt source.
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Must be a single cell with a value of at least 3.
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If the system requires describing PPI affinity, then the value must
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be at least 4.
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The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
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interrupts, 2 for interrupts in the Extended SPI range, 3 for the
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Extended PPI range. Other values are reserved for future use.
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The 2nd cell contains the interrupt number for the interrupt type.
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SPI interrupts are in the range [0-987]. PPI interrupts are in the
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range [0-15]. Extented SPI interrupts are in the range [0-1023].
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Extended PPI interrupts are in the range [0-127].
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The 3rd cell is the flags, encoded as follows:
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bits[3:0] trigger type and level flags.
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1 = edge triggered
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4 = level triggered
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The 4th cell is a phandle to a node describing a set of CPUs this
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interrupt is affine to. The interrupt must be a PPI, and the node
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pointed must be a subnode of the "ppi-partitions" subnode. For
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interrupt types other than PPI or PPIs that are not partitionned,
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this cell must be zero. See the "ppi-partitions" node description
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below.
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Cells 5 and beyond are reserved for future use and must have a value
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of 0 if present.
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enum: [ 3, 4 ]
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reg:
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description: |
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Specifies base physical address(s) and size of the GIC
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registers, in the following order:
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- GIC Distributor interface (GICD)
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- GIC Redistributors (GICR), one range per redistributor region
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- GIC CPU interface (GICC)
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- GIC Hypervisor interface (GICH)
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- GIC Virtual CPU interface (GICV)
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GICC, GICH and GICV are optional, but must be described if the CPUs
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support them. Examples of such CPUs are ARM's implementations of the
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ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
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A73 (this list is not exhaustive).
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minItems: 2
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maxItems: 4096 # Should be enough?
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interrupts:
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description:
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Interrupt source of the VGIC maintenance interrupt.
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maxItems: 1
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redistributor-stride:
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description:
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If using padding pages, specifies the stride of consecutive
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redistributors. Must be a multiple of 64kB.
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$ref: /schemas/types.yaml#/definitions/uint64
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multipleOf: 0x10000
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exclusiveMinimum: 0
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"#redistributor-regions":
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description:
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The number of independent contiguous regions occupied by the
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redistributors. Required if more than one such region is present.
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$ref: /schemas/types.yaml#/definitions/uint32
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maximum: 4096
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msi-controller:
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description:
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Only present if the Message Based Interrupt functionnality is
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being exposed by the HW, and the mbi-ranges property present.
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mbi-ranges:
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description:
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A list of pairs <intid span>, where "intid" is the first SPI of a range
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that can be used an MBI, and "span" the size of that range. Multiple
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ranges can be provided.
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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items:
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minItems: 2
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maxItems: 2
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mbi-alias:
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description:
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Address property. Base address of an alias of the GICD region containing
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only the {SET,CLR}SPI registers to be used if isolation is required,
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and if supported by the HW.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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minItems: 1
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maxItems: 2
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ppi-partitions:
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type: object
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description:
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PPI affinity can be expressed as a single "ppi-partitions" node,
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containing a set of sub-nodes.
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patternProperties:
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"^interrupt-partition-[0-9]+$":
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type: object
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properties:
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affinity:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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maxItems: 1
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description:
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Should be a list of phandles to CPU nodes (as described in
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Documentation/devicetree/bindings/arm/cpus.yaml).
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required:
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- affinity
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: aclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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dependencies:
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mbi-ranges: [ msi-controller ]
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msi-controller: [ mbi-ranges ]
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required:
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- compatible
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- interrupts
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- reg
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patternProperties:
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"^gic-its@": false
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"^interrupt-controller@[0-9a-f]+$": false
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# msi-controller is preferred, but allow other names
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"^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
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type: object
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description:
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GICv3 has one or more Interrupt Translation Services (ITS) that are
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used to route Message Signalled Interrupts (MSI) to the CPUs.
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properties:
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compatible:
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const: arm,gic-v3-its
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msi-controller: true
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"#msi-cells":
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description:
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The single msi-cell is the DeviceID of the device which will generate
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the MSI.
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const: 1
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reg:
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description:
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Specifies the base physical address and size of the ITS registers.
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maxItems: 1
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socionext,synquacer-pre-its:
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description:
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(u32, u32) tuple describing the untranslated
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address and size of the pre-ITS window.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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items:
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minItems: 2
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maxItems: 2
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required:
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- compatible
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- msi-controller
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- "#msi-cells"
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- reg
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additionalProperties: false
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additionalProperties: false
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examples:
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- |
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gic: interrupt-controller@2cf00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller;
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reg = <0x2f000000 0x10000>, // GICD
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<0x2f100000 0x200000>, // GICR
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<0x2c000000 0x2000>, // GICC
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<0x2c010000 0x2000>, // GICH
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<0x2c020000 0x2000>; // GICV
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interrupts = <1 9 4>;
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msi-controller;
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mbi-ranges = <256 128>;
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msi-controller@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x2c200000 0x20000>;
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};
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};
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- |
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interrupt-controller@2c010000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller;
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redistributor-stride = <0x0 0x40000>; // 256kB stride
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#redistributor-regions = <2>;
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reg = <0x2c010000 0x10000>, // GICD
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<0x2d000000 0x800000>, // GICR 1: CPUs 0-31
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<0x2e000000 0x800000>, // GICR 2: CPUs 32-63
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<0x2c040000 0x2000>, // GICC
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<0x2c060000 0x2000>, // GICH
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<0x2c080000 0x2000>; // GICV
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interrupts = <1 9 4 0>;
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msi-controller@2c200000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x2c200000 0x20000>;
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};
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msi-controller@2c400000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x2c400000 0x20000>;
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};
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ppi-partitions {
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part0: interrupt-partition-0 {
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affinity = <&cpu0>, <&cpu2>;
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};
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part1: interrupt-partition-1 {
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affinity = <&cpu1>, <&cpu3>;
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};
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};
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};
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device@0 {
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reg = <0 4>;
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interrupts = <1 1 4 &part0>;
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};
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...
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