c20f80d0b8
The Allwinner A31 MIPI D-PHY block supports both tx and rx directions, although each instance of the block is meant to be used in one direction only. There will typically be one instance for MIPI DSI and one for MIPI CSI-2 (it seems unlikely to ever see a shared instance). Describe the direction with a new allwinner,direction property. For backwards compatibility, the property is optional and tx mode should be assumed by default. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220415152138.635525-2-paul.kocialkowski@bootlin.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
74 lines
1.4 KiB
YAML
74 lines
1.4 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A31 MIPI D-PHY Controller Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <wens@csie.org>
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- Maxime Ripard <mripard@kernel.org>
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properties:
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"#phy-cells":
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const: 0
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compatible:
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oneOf:
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- const: allwinner,sun6i-a31-mipi-dphy
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- items:
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- const: allwinner,sun50i-a64-mipi-dphy
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- const: allwinner,sun6i-a31-mipi-dphy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: Bus Clock
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- description: Module Clock
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clock-names:
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items:
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- const: bus
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- const: mod
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resets:
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maxItems: 1
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allwinner,direction:
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$ref: '/schemas/types.yaml#/definitions/string'
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description: |
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Direction of the D-PHY:
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- "rx" for receiving (e.g. when used with MIPI CSI-2);
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- "tx" for transmitting (e.g. when used with MIPI DSI).
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enum:
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- tx
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- rx
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default: tx
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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additionalProperties: false
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examples:
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- |
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dphy0: d-phy@1ca1000 {
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compatible = "allwinner,sun6i-a31-mipi-dphy";
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reg = <0x01ca1000 0x1000>;
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clocks = <&ccu 23>, <&ccu 97>;
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clock-names = "bus", "mod";
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resets = <&ccu 4>;
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#phy-cells = <0>;
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};
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...
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