be215b9270
The Meson Timer IP has two clock inputs: - pclk which is used as "system clock" timebase of Timer E - xtal which is used for the 1us, 10us, 100us and 1ms timebases of Timer A, B, C, D and E The IP block has four internal dividers (XTAL is running at 24MHz): - "xtal div 24" for 1us resolution - "xtal div 240" for 10us resolution - "xtal div 2400" for 100us resolution - "xtal div 24000" for 1ms resolution Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
23 lines
675 B
Plaintext
23 lines
675 B
Plaintext
Amlogic Meson6 SoCs Timer Controller
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Required properties:
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- compatible : should be "amlogic,meson6-timer"
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- reg : Specifies base physical address and size of the registers.
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- interrupts : The four interrupts, one for each timer event
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- clocks : phandles to the pclk (system clock) and XTAL clocks
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- clock-names : must contain "pclk" and "xtal"
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Example:
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timer@c1109940 {
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compatible = "amlogic,meson6-timer";
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reg = <0xc1109940 0x14>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 11 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 6 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
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clocks = <&xtal>, <&clk81>;
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clock-names = "xtal", "pclk";
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};
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