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linux/drivers/clk/tegra
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JC Kuo 0c7ea2b1c8 clk: tegra: Don't enable PLLE HW sequencer at init 
PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware
power sequencers' output to enable/disable PLLE. PLLE hardware power
sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers
are enabled.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2021-03-24 14:02:14 +01:00
..
clk-audio-sync.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
2019-05-30 11:29:52 -07:00
clk-bpmp.c
clk: tegra: bpmp: Clamp clock rates on requests
2020-11-26 16:28:07 +01:00
clk-dfll.c
clk: tegra: Do not return 0 on failure
2020-11-20 17:19:46 +01:00
clk-dfll.h
clk: tegra: clk-dfll: Add suspend and resume support
2019-11-11 14:53:03 +01:00
clk-divider.c
clk: tegra: divider: Check UART's divider enable-bit state on rate's recalculation
2020-01-10 15:50:05 +01:00
clk-id.h
clk: tegra: Fix duplicated SE clock entry
2020-12-10 12:51:59 -08:00
clk-periph-fixed.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
2019-05-30 11:29:52 -07:00
clk-periph-gate.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
2019-05-30 11:29:52 -07:00
clk-periph.c
clk: tegra: periph: Add restore_context support
2019-11-11 14:53:02 +01:00
clk-pll-out.c
clk: tegra: pllout: Save and restore pllout context
2019-11-11 14:53:02 +01:00
clk-pll.c
clk: tegra: Don't enable PLLE HW sequencer at init
2021-03-24 14:02:14 +01:00
clk-sdmmc-mux.c
clk: tegra: periph: Add restore_context support
2019-11-11 14:53:02 +01:00
clk-super.c
clk: tegra: clk-super: Add restore-context support
2019-11-11 14:53:03 +01:00
clk-tegra20-emc.c
clk: tegra: Export Tegra20 EMC kernel symbols
2020-11-06 19:24:04 +01:00
clk-tegra20.c
clk: tegra20: Use custom CCLK implementation
2020-05-12 22:48:43 +02:00
clk-tegra30.c
This is all driver updates, the majority of which is a bunch of new Qualcomm
2021-02-22 09:45:23 -08:00
clk-tegra114.c
clk: tegra: Remove audio clocks configuration from clock driver
2020-03-12 12:10:49 +01:00
clk-tegra124-dfll-fcpu.c
clk: tegra: clk-dfll: Add suspend and resume support
2019-11-11 14:53:03 +01:00
clk-tegra124-emc.c
memory: tegra124-emc: Make driver modular
2021-01-05 18:00:09 +01:00
clk-tegra124.c
memory: tegra124-emc: Make driver modular
2021-01-05 18:00:09 +01:00
clk-tegra210-emc.c
This pull request contains zero diff to the core framework. It is a collection
2020-10-22 12:53:28 -07:00
clk-tegra210.c
clk: tegra: Add PLLE HW power sequencer control
2021-03-24 14:01:58 +01:00
clk-tegra-audio.c
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201
2019-05-30 11:29:52 -07:00
clk-tegra-fixed.c
clk: tegra: Remove CLK_M_DIV fixed clocks
2020-03-12 11:33:32 +01:00
clk-tegra-periph.c
clk: tegra: Fix duplicated SE clock entry
2020-12-10 12:51:59 -08:00
clk-tegra-super-cclk.c
clk: tegra: cclk: Add helpers for handling PLLX rate changes
2020-05-12 22:48:43 +02:00
clk-tegra-super-gen4.c
clk: tegra: clk-super: Fix to enable PLLP branches to CPU
2019-11-11 14:53:03 +01:00
clk-utils.c
clk: tegra: Refactor fractional divider calculation
2018-07-25 13:43:34 -07:00
clk.c
clk: tegra: Fix double-free in tegra_clk_init()
2019-12-24 00:01:06 -08:00
clk.h
memory: tegra124-emc: Make driver modular
2021-01-05 18:00:09 +01:00
cvb.c
clk: tegra: cvb: Provide missing description for 'tegra_cvb_add_opp_table()'s align param
2021-02-11 11:56:05 -08:00
cvb.h
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174
2019-05-30 11:26:41 -07:00
Kconfig
memory: tegra124-emc: Make driver modular
2021-01-05 18:00:09 +01:00
Makefile
memory: tegra124-emc: Make driver modular
2021-01-05 18:00:09 +01:00