linux/drivers/phy/qualcomm
Stephen Boyd aa968cb1a6 phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy'
The serdes I/O region is where the PLL for the phy is controlled.
Sometimes the PLL is shared between multiple phys, for example in the
PCIe case where there are three phys inside the same wrapper. Other
times the PLL is for a single phy, i.e. some USB3 phys. To complete the
trifecta we have the USB3+DP combo phy where the USB3 and DP phys each
have their own serdes region because they have their own PLL while they
both share a common I/O region pertaining to the USB type-c pinout and
cable orientation.

Let's move the serdes iomem pointer into 'struct qmp_phy' so that we can
correlate PLL control to the phy that uses it. This allows us to support
the USB3+DP combo phy in this driver. This isn't a problem for the
3-lane/phy PCIe phy because there is a common init function that is the
only place the serdes region is programmed.

Furthermore, move the configuration data that contains most of the
register programming sequences to the qmp phy struct. This data isn't
qmp wrapper specific. It is phy specific data used to tune various
settings for things like pre-emphasis, bias, etc.

Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Cc: Jeykumar Sankaran <jsanka@codeaurora.org>
Cc: Chandan Uddaraju <chandanu@codeaurora.org>
Cc: Vara Reddy <varar@codeaurora.org>
Cc: Tanmay Shah <tanmay@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Manu Gautam <mgautam@codeaurora.org>
Cc: Sandeep Maheswaram <sanm@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Jonathan Marek <jonathan@marek.ca>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: Rob Clark <robdclark@chromium.org>
Link: https://lore.kernel.org/r/20200916231202.3637932-5-swboyd@chromium.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2020-09-28 11:27:53 +05:30
..
Kconfig phy: qualcomm: add qcom ipq806x dwc usb phy driver 2020-07-20 11:54:03 +05:30
Makefile phy: qualcomm: add qcom ipq806x dwc usb phy driver 2020-07-20 11:54:03 +05:30
phy-ath79-usb.c phy: ath79-usb: Fix the main reset name to match the DT binding 2019-01-16 18:00:57 +05:30
phy-qcom-apq8064-sata.c phy: phy-qcom-apq8064-sata: convert to readl_relaxed_poll_timeout() 2020-09-08 09:56:11 +05:30
phy-qcom-ipq806x-sata.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284 2019-06-05 17:36:37 +02:00
phy-qcom-ipq806x-usb.c phy: qualcomm: fix return value check in qcom_ipq806x_usb_phy_probe() 2020-08-17 09:37:12 +05:30
phy-qcom-ipq4019-usb.c phy: qcom-ipq4019-usb: Constify static phy_ops structs 2020-08-31 14:36:37 +05:30
phy-qcom-pcie2.c phy: qcom: Add Qualcomm PCIe2 PHY driver 2019-05-31 19:41:13 +05:30
phy-qcom-qmp.c phy: qcom-qmp: Move 'serdes' and 'cfg' into 'struct qcom_phy' 2020-09-28 11:27:53 +05:30
phy-qcom-qmp.h phy: qcom-qmp: Use correct values for ipq8074 PCIe Gen2 PHY init 2020-08-23 21:20:14 +05:30
phy-qcom-qusb2.c phy: qcom-qusb2: Add ipq8074 device compatible 2020-06-24 22:48:00 +05:30
phy-qcom-snps-femto-v2.c phy: qcom-snps: Add a set mode callback 2020-06-29 15:15:56 +05:30
phy-qcom-usb-hs-28nm.c phy: qualcomm: usb-hs-28nm: Prepare clocks in init 2020-04-30 12:10:49 +05:30
phy-qcom-usb-hs.c phy: qcom-usb-hs: Fix extcon double register after power cycle 2019-10-31 16:54:01 +05:30
phy-qcom-usb-hsic.c treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 2019-06-19 17:09:55 +02:00
phy-qcom-usb-ss.c phy: qualcomm: usb: Add SuperSpeed PHY driver 2020-03-20 19:34:29 +05:30