d6d0c7f681
CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some new performance monitoring features for AMD processors. Bit 0 of EAX indicates support for Performance Monitoring Version 2 (PerfMonV2) features. If found to be set during PMU initialization, the EBX bits of the same CPUID function can be used to determine the number of available PMCs for different PMU types. Additionally, Core PMCs can be managed using new global control and status registers. For better utilization of feature words, PerfMonV2 is added as a scattered feature bit. Signed-off-by: Sandipan Das <sandipan.das@amd.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/c70e497e22f18e7f05b025bb64ca21cc12b17792.1650515382.git.sandipan.das@amd.com
72 lines
2.2 KiB
C
72 lines
2.2 KiB
C
/*
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* Routines to identify additional cpu features that are scattered in
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* cpuid space.
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*/
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#include <linux/cpu.h>
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#include <asm/memtype.h>
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#include <asm/apic.h>
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#include <asm/processor.h>
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#include "cpu.h"
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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u8 bit;
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u32 level;
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u32 sub_leaf;
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};
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/*
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* Please keep the leaf sorted by cpuid_bit.level for faster search.
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* X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
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* levels are different and there is a separate entry for each.
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*/
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static const struct cpuid_bit cpuid_bits[] = {
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{ X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
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{ X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
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{ X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
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{ X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
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{ X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
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{ X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
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{ X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
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{ X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
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{ X86_FEATURE_CAT_L2, CPUID_EBX, 2, 0x00000010, 0 },
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{ X86_FEATURE_CDP_L3, CPUID_ECX, 2, 0x00000010, 1 },
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{ X86_FEATURE_CDP_L2, CPUID_ECX, 2, 0x00000010, 2 },
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{ X86_FEATURE_MBA, CPUID_EBX, 3, 0x00000010, 0 },
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{ X86_FEATURE_PER_THREAD_MBA, CPUID_ECX, 0, 0x00000010, 3 },
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{ X86_FEATURE_SGX1, CPUID_EAX, 0, 0x00000012, 0 },
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{ X86_FEATURE_SGX2, CPUID_EAX, 1, 0x00000012, 0 },
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{ X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 },
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{ X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 },
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{ X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 },
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{ X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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{
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u32 max_level;
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u32 regs[4];
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const struct cpuid_bit *cb;
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for (cb = cpuid_bits; cb->feature; cb++) {
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/* Verify that the level is valid */
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max_level = cpuid_eax(cb->level & 0xffff0000);
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if (max_level < cb->level ||
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max_level > (cb->level | 0xffff))
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continue;
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cpuid_count(cb->level, cb->sub_leaf, ®s[CPUID_EAX],
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®s[CPUID_EBX], ®s[CPUID_ECX],
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®s[CPUID_EDX]);
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if (regs[cb->reg] & (1 << cb->bit))
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set_cpu_cap(c, cb->feature);
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}
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}
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