0bbc9bc318
The SH7780 PCI host controller implements a configuration header that requires a fair bit of hand-holding to initialize properly. By default it appears as a pre-2.0 host controller given the zeroed out class code, so fix this up properly. Some boards that happened to be using the R7780RP version of the PCIC fixups had set this correctly, but this belongs in the standard initialization, and is by no means board specific. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*
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* arch/sh/drivers/pci/fixups-sdk7780.c
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*
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* PCI fixups for the SDK7780SE03
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*
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* Copyright (C) 2003 Lineo uSolutions, Inc.
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* Copyright (C) 2004 - 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/pci.h>
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#include "pci-sh4.h"
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#include <asm/io.h>
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int pci_fixup_pcic(struct pci_channel *chan)
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{
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/* Enable all interrupts, so we know what to fix */
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pci_write_reg(chan, 0x0000C3FF, SH7780_PCIIMR);
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pci_write_reg(chan, 0x0000380F, SH7780_PCIAINTM);
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/* Set up standard PCI config registers */
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pci_write_reg(chan, 0xFB00, SH7780_PCISTATUS);
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pci_write_reg(chan, 0x0047, SH7780_PCICMD);
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pci_write_reg(chan, 0x00, SH7780_PCIPIF);
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pci_write_reg(chan, 0x1912, SH7780_PCISVID);
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pci_write_reg(chan, 0x0001, SH7780_PCISID);
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pci_write_reg(chan, 0x08000000, SH7780_PCIMBAR0); /* PCI */
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pci_write_reg(chan, 0x08000000, SH7780_PCILAR0); /* SHwy */
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pci_write_reg(chan, 0x07F00001, SH7780_PCILSR); /* size 128M w/ MBAR */
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pci_write_reg(chan, 0x00000000, SH7780_PCIMBAR1);
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pci_write_reg(chan, 0x00000000, SH7780_PCILAR1);
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pci_write_reg(chan, 0x00000000, SH7780_PCILSR1);
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pci_write_reg(chan, 0xAB000801, SH7780_PCIIBAR);
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/*
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* Set the MBR so PCI address is one-to-one with window,
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* meaning all calls go straight through... use ifdef to
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* catch erroneous assumption.
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*/
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pci_write_reg(chan, 0xFD000000 , SH7780_PCIMBR0);
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pci_write_reg(chan, 0x00FC0000 , SH7780_PCIMBMR0); /* 16M */
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/* Set IOBR for window containing area specified in pci.h */
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pci_write_reg(chan, chan->io_resource->start & ~(SH7780_PCI_IO_SIZE-1),
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SH7780_PCIIOBR);
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pci_write_reg(chan, (SH7780_PCI_IO_SIZE-1) & (7 << 18),
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SH7780_PCIIOBMR);
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pci_write_reg(chan, 0xA5000C01, SH7780_PCICR);
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return 0;
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}
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