740fbddf5c
The current sp5100_tco driver only supports SP5100/SB7x0 chipset, doesn't
support SB8x0 chipset, because current sp5100_tco driver doesn't know that the
offset address for watchdog timer was changed from SB8x0 chipset.
The offset address of SP5100 and SB7x0 chipsets are as follows, quote from the
AMD SB700/710/750 Register Reference Guide (Page 164) and the AMD SP5100
Register Reference Guide (Page 166).
WatchDogTimerControl 69h
WatchDogTimerBase0 6Ch
WatchDogTimerBase1 6Dh
WatchDogTimerBase2 6Eh
WatchDogTimerBase3 6Fh
In contrast, the offset address of SB8x0 chipset is as follows, quote from
AMD SB800-Series Southbridges Register Reference Guide (Page 147).
WatchDogTimerEn 48h
WatchDogTimerConfig 4Ch
So, In the case of SB8x0 chipset, sp5100_tco reads meaningless MMIO
address (for example, 0xbafe00) from wrong offset address, and the following
message is logged.
SP5100 TCO timer: mmio address 0xbafe00 already in use
With this patch, sp5100_tco driver supports SB8x0 chipset, and can avoid
iomem resource conflict. The processing of this patch is as follows.
Step 1) Attempt to get the watchdog base address from indirect I/O (0xCD6
and 0xCD7).
- Go to the step 7 if obtained address hasn't conflicted with other
resource. But, currently, the address (0xfec000f0) conflicts with the
IOAPIC MMIO address, and the following message is logged.
SP5100 TCO timer: mmio address 0xfec000f0 already in use
0xfec000f0 is recommended by AMD BIOS Developer's Guide. So, go to the
next step.
Step 2) Attempt to get the SBResource_MMIO base address from AcpiMmioEN (for
SB8x0, PM_Reg:24h) or SBResource_MMIO (SP5100/SB7x0, PCI_Reg:9Ch)
register.
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- If above condition isn't true, go to the next step.
Step 3) Attempt to get the free MMIO address from allocate_resource().
- Go to the step 7 if these register has enabled by BIOS, and obtained
address hasn't conflicted with other resource.
- Driver initialization has failed if obtained address has conflicted
with other resource, and no 'force_addr' parameter is specified.
Step 4) Use the specified address If 'force_addr' parameter is specified.
- allocate_resource() function may fail, when the PCI bridge device occupies
iomem resource from 0xf0000000 to 0xffffffff. To handle such a case,
I added 'force_addr' parameter to sp5100_tco driver. With 'force_addr'
parameter, sp5100_tco driver directly can assign MMIO address for watchdog
timer from free iomem region. Note that It's dangerous to specify wrong
address in the 'force_addr' parameter.
Example of force_addr parameter use
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
<--- free MMIO region
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
# cat /etc/modprobe.d/sp5100_tco.conf
options sp5100_tco force_addr=0xfec00800
# modprobe sp5100_tco
# cat /proc/iomem
...snip...
fec00000-fec003ff : IOAPIC 0
fec00800-fec00807 : SP5100 TCO <--- watchdog timer MMIO address
fec10000-fec1001f : pnp 00:0b
fec20000-fec203ff : IOAPIC 1
...snip...
#
- Driver initialization has failed if specified address has conflicted
with other resource.
Step 5) Disable the watchdog timer
- To rewrite the watchdog timer register of the chipset, absolutely
guarantee that the watchdog timer is disabled.
Step 6) Re-program the watchdog timer MMIO address to chipset.
- Re-program the obtained MMIO address in Step 3 or Step 4 to chipset via
indirect I/O (0xCD6 and 0xCD7).
Step 7) Enable and setup the watchdog timer
This patch has worked fine on my test environment (ASUS M4A89GTD-PRO/USB3 and
DL165G7). therefore I believe that it's no problem to re-program the MMIO
address for watchdog timer to chipset during disabled watchdog. However,
I'm not sure about it, because I don't know much about chipset programming.
So, any comments will be welcome.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43176
Tested-by: Arkadiusz Miskiewicz <arekm@maven.pl>
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Takahisa Tanaka <mc74hc00@gmail.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/*
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* sp5100_tco: TCO timer driver for sp5100 chipsets.
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*
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* (c) Copyright 2009 Google Inc., All Rights Reserved.
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*
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* TCO timer driver for sp5100 chipsets
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*/
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/*
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* Some address definitions for the Watchdog
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*/
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#define SP5100_WDT_MEM_MAP_SIZE 0x08
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#define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */
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#define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */
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#define SP5100_WDT_START_STOP_BIT (1 << 0)
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#define SP5100_WDT_TRIGGER_BIT (1 << 7)
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#define SP5100_PM_IOPORTS_SIZE 0x02
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/*
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* These two IO registers are hardcoded and there doesn't seem to be a way to
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* read them from a register.
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*/
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/* For SP5100/SB7x0 chipset */
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#define SP5100_IO_PM_INDEX_REG 0xCD6
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#define SP5100_IO_PM_DATA_REG 0xCD7
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#define SP5100_SB_RESOURCE_MMIO_BASE 0x9C
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#define SP5100_PM_WATCHDOG_CONTROL 0x69
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#define SP5100_PM_WATCHDOG_BASE 0x6C
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#define SP5100_PM_WATCHDOG_FIRED (1 << 1)
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#define SP5100_PM_WATCHDOG_ACTION_RESET (1 << 2)
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#define SP5100_PCI_WATCHDOG_MISC_REG 0x41
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#define SP5100_PCI_WATCHDOG_DECODE_EN (1 << 3)
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#define SP5100_PM_WATCHDOG_DISABLE (1 << 0)
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#define SP5100_PM_WATCHDOG_SECOND_RES (3 << 1)
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#define SP5100_DEVNAME "SP5100 TCO"
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/* For SB8x0(or later) chipset */
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#define SB800_IO_PM_INDEX_REG 0xCD6
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#define SB800_IO_PM_DATA_REG 0xCD7
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#define SB800_PM_ACPI_MMIO_EN 0x24
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#define SB800_PM_WATCHDOG_CONTROL 0x48
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#define SB800_PM_WATCHDOG_BASE 0x48
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#define SB800_PM_WATCHDOG_CONFIG 0x4C
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#define SB800_PCI_WATCHDOG_DECODE_EN (1 << 0)
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#define SB800_PM_WATCHDOG_DISABLE (1 << 2)
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#define SB800_PM_WATCHDOG_SECOND_RES (3 << 0)
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#define SB800_ACPI_MMIO_DECODE_EN (1 << 0)
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#define SB800_ACPI_MMIO_SEL (1 << 2)
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#define SB800_PM_WDT_MMIO_OFFSET 0xB00
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#define SB800_DEVNAME "SB800 TCO"
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