86d11e225e
For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> |
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Kconfig | ||
Makefile | ||
phy-am654-serdes.c | ||
phy-da8xx-usb.c | ||
phy-dm816x-usb.c | ||
phy-gmii-sel.c | ||
phy-j721e-wiz.c | ||
phy-omap-control.c | ||
phy-omap-usb2.c | ||
phy-ti-pipe3.c | ||
phy-tusb1210.c | ||
phy-twl4030-usb.c |