Chris Metcalf acbde1db29 tile: parameterize VA and PA space more cleanly ...

The existing code relied on the hardware definition (<arch/chip.h>)
to specify how much VA and PA space was available.  It's convenient
to allow customizing this for some configurations, so provide symbols
MAX_PA_WIDTH and MAX_VA_WIDTH in <asm/page.h> that can be modified
if desired.

Additionally, move away from the MEM_XX_INTRPT nomenclature to
define the start of various regions within the VA space.  In fact
the cleaner symbol is, for example, MEM_SV_START, to indicate the
start of the area used for supervisor code; the actual address of the
interrupt vectors is not as important, and can be changed if desired.
As part of this change, convert from "intrpt1" nomenclature (which
built in the old privilege-level 1 model) to a simple "intrpt".

Also strip out some tilepro-specific code supporting modifying the
PL the kernel could run at, since we don't actually support using
different PLs in tilepro, only tilegx.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

2013-09-03 14:47:34 -04:00

..

arch

tile PCI RC: support more MSI-X interrupt vectors

2013-08-06 12:55:24 -04:00

asm

tile: parameterize VA and PA space more cleanly

2013-09-03 14:47:34 -04:00

gxio

tile PCI RC: support more MSI-X interrupt vectors

2013-08-06 12:55:24 -04:00

hv

tile: improve big-endian support

2013-08-13 16:26:05 -04:00

uapi

tile: support kprobes on tilegx

2013-08-30 11:55:53 -04:00