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linux/drivers/gpu/drm/amd/display/dc/dcn20
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Anthony Koo bbf5f6c3f8 drm/amd/display: Split program front end part that occur outside lock 
[Why]
Eventually want to lock at a higher level in stack.
To do this, we need to be able to isolate the parts that need to be done
after pipe unlock.

[How]
Split out programming that is done post unlock.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-02-06 15:04:36 -05:00
..
dcn20_dccg.c
drm/amd/display: Formula refactor for calculating DPP CLK DTO
2019-12-18 16:09:10 -05:00
dcn20_dccg.h
drm/amd/display: Revert fixup DPP programming sequence
2019-10-03 09:10:51 -05:00
dcn20_dpp_cm.c
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_dpp.c
drm/amd/display: Double buffer dcn2 Gamut Remap
2020-01-16 14:13:30 -05:00
dcn20_dpp.h
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_dsc.c
drm/amd/display: Initialize DSC PPS variables to 0
2020-01-09 18:07:47 -05:00
dcn20_dsc.h
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
2019-11-13 15:29:44 -05:00
dcn20_dwb_scl.c
drm/amd/display: Remove set but not used variables 'h_ratio_chroma', 'v_ratio_chroma'
2019-10-07 15:10:43 -05:00
dcn20_dwb.c
…
dcn20_dwb.h
…
dcn20_hubbub.c
drm/amd/display: Add default switch case for DCC
2020-01-16 14:15:42 -05:00
dcn20_hubbub.h
drm/amd/display: Add detile buffer size for DCN20
2019-10-03 09:10:58 -05:00
dcn20_hubp.c
drm/amd/display: Wrong ifdef guards were used around DML validation
2019-12-05 16:27:16 -05:00
dcn20_hubp.h
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flag
2019-11-13 15:29:44 -05:00
dcn20_hwseq.c
drm/amd/display: Split program front end part that occur outside lock
2020-02-06 15:04:36 -05:00
dcn20_hwseq.h
drm/amd/display: Split program front end part that occur outside lock
2020-02-06 15:04:36 -05:00
dcn20_init.c
drm/amd/display: Split program front end part that occur outside lock
2020-02-06 15:04:36 -05:00
dcn20_init.h
drm/amd/display: cleanup of function pointer tables
2019-11-19 10:12:53 -05:00
dcn20_link_encoder.c
drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTED
2019-11-13 15:29:44 -05:00
dcn20_link_encoder.h
drm/amd/display: add missing dcn link encoder regs
2019-12-18 16:09:06 -05:00
dcn20_mmhubbub.c
…
dcn20_mmhubbub.h
…
dcn20_mpc.c
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_mpc.h
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_opp.c
drm/amd/display: add color space option when sending link test pattern
2019-11-19 10:12:52 -05:00
dcn20_opp.h
drm/amd/display: add color space option when sending link test pattern
2019-11-19 10:12:52 -05:00
dcn20_optc.c
drm/amd/display: Fix manual trigger source for DCN2
2019-12-18 16:09:10 -05:00
dcn20_optc.h
drm/amd/display: Fix manual trigger source for DCN2
2019-12-18 16:09:10 -05:00
dcn20_resource.c
drm/amd/display: Indirect reg read macro with shift and mask
2020-01-16 14:13:53 -05:00
dcn20_resource.h
drm/amd/display: MST DSC compute fair share
2020-01-09 18:07:47 -05:00
dcn20_stream_encoder.c
drm/amd/display: Reset steer fifo before unblanking the stream
2019-12-05 18:19:54 -05:00
dcn20_stream_encoder.h
drm/amd/display: set MSA MISC1 bit 6 while sending colorimetry in VSC SDP
2019-11-13 15:29:43 -05:00
dcn20_vmid.c
drm/amd/display: Poll for GPUVM context ready (v2)
2019-07-18 14:18:09 -05:00
dcn20_vmid.h
…
Makefile
amdgpu: Enable initial DCN support on POWER
2019-12-18 16:09:05 -05:00