868a11b602
Highlights:
----------
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35,
common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
This PR adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA7FiEEctl9+nxzUSUqdELdf5rJavIecIUFAmSG5+AdHGFsZXhhbmRy
ZS50b3JndWVAZm9zcy5zdC5jb20ACgkQf5rJavIecIUXEA/4mb17fH6BUDc1wGHb
kl7XJh8s9A98Wbjlei+fgZ6VfDRU1KuEkna/TJ+8QwBadb450RSPxCozWyaT94kq
EeVHw2pyQELBA7T4Cu/3OzyD2dQj/hELbWKlUT5UedMibguxYb+IyxMqOrw29Ghb
t5G1cfJknkbXQDKrEVDynUHoRcDIb3vLXhvL3Z8ExSDBaaVdhrpXyJow4fRBUgtY
gqEnVJHOVHsu5k+Ah2/2SaMUpxfQIUduxFMsk7pAFiZU+nRQI03Cn6EKADCIgmS0
1LZVhjfO15Tm5X2bDN+gHqC+3ASZGZqe4KkUF5RfIN+2K1Jo8CMCoezHga0y03Lb
EN6PEoHhriqNs/2azFLTQbua0RzkdJxXNNWAG5I+I0qim6hicTV9YCkkxIQlhNxu
K67BdvBEJrDNBYlkk4DDaiGRuPFSoitwYMnZqCrvLGtxtTbjrMjppCCvdJPrCGBr
aY/1hLePnnxdBvCFKODKkiAT48gPjZoEhLrbegIY2XMqseciX4o9JZbXmnMVdpqD
2l1M2xsyVe5Jxv8JRfnr6GfUj0FVIgxB8tUII7OpXxTGZN9MaOt/92DKTbvLdvma
MwIOIMKB5QYFytCNwjFMI2LJopfiFJNUKk2Yd+WNWGaEG1LmdhTSIIROQBMDM5Zg
xTR+DvbdtbgyTSSsuBDGw1UWnA==
=WkNC
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSSC/wACgkQYKtH/8kJ
UidpWhAAn9bQwdIJdetMmMiJuvFJIqPg48K9OmvEpEYCxAwVFuKTV+ddGDM2kLwB
rinJ5R92FsCUBN54mPpfq75atuhZA8S3Od4N8jbjK7Geqq0MIUv6yaGYNyKJfDrx
NO3+UzIpF17eqiXDTY4ZEdw+FfWJ1fr1rKN2DNyqIQDIibvOR8smuAE9suIdNsht
0k0LOCk+PXRaNws6wIeXM71v42trb8S5UG02qQzet1qwsK7OXUc7xouTr6vQ7xMR
H4NiuEL0XfkhsxsSLhbFSpWzRoVcKhhyZzibNu4l5npBvL0VZPyYrJOU7MAODy5D
IWIS07/BNWrKx/XhCyz7w0ID2SsMGxAgGeOMx1eG3WT5953z5tWOqBgZGWrObQMO
QR4F2h+f9InLblHEdLa+n1Nfm6SAgGEA+JnDDHSbuiH1t/g01wazxCAi6Awoxur6
jv7iINiy2UauRs7/Fns0z1J0gag/8afxTYiEzBQSMdrE4zgaKKGtryoflUOXZe9W
foXtU4+mRAExrZN/3gxYQyvvLxQF7vllCYtuzeUyJzpXuYwE5clpjjEn93txXtPr
EjIS+fg3cgABaD26607ueGomQIdKxjWj/1tZSaut1yWs/zeuRjS15dT68IzzI0mK
Qk1v6mLx+gdnOQv8mn5JfzOC8MTDBrAE53B6M+mI9nZrV3VhhhE=
=fxHg
-----END PGP SIGNATURE-----
Merge tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/newsoc
STM32 STM32MP25 for v6.5, round 1
Highlights:
----------
STM32MP25 family is composed of 4 SoCs defined as following:
-STM32MP251: common part composed of 1*Cortex-A35,
common peripherals like SDMMC, UART, SPI, I2C, PCIe, USB3,
parallel and DSI display, 1*ETH ...
-STM32MP253: STM32MP251 + 1*Cortex-A35 (dual CPU), a second ETH,
CAN-FD and LVDS display.
-STM32MP255: STM32MP253 + GPU/AI and video encode/decode.
-STM32MP257: STM32MP255 + ETH TSN switch (2+1 ports).
A second diversity layer exists for security features/A35 frequency:
-STM32MP25xY, "Y" gives information:
-Y = A means A35@1.2GHz + no cryp IP and no secure boot.
-Y = C means A35@1.2GHz + cryp IP and secure boot.
-Y = D means A35@1.5GHz + no cryp IP and no secure boot.
-Y = F means A35@1.5GHz + cryp IP and secure boot.
This PR adds the STM32MP257F EV1 board support. This board embeds a
STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports),
2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
* tag 'stm32-mp25-for-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: (44 commits)
MAINTAINERS: add entry for ARM/STM32 ARCHITECTURE
arm64: defconfig: enable ARCH_STM32 and STM32 serial driver
arm64: dts: st: add stm32mp257f-ev1 board support
dt-bindings: stm32: document stm32mp257f-ev1 board
arm64: dts: st: introduce stm32mp25 pinctrl files
arm64: dts: st: introduce stm32mp25 SoCs family
arm64: introduce STM32 family on Armv8 architecture
dt-bindings: stm32: add st,stm32mp25-syscfg compatible for syscon
pinctrl: stm32: add stm32mp257 pinctrl support
dt-bindings: pinctrl: stm32: support for stm32mp257 and additional packages
ARM: dts: stm32: fix i2s endpoint format property for stm32mp15xx-dkx
ARM: dts: stm32: Fix audio routing on STM32MP15xx DHCOM PDK2
ARM: dts: stm32: add required supplies of ov5640 in stm32mp157c-ev1
ARM: dts: stm32: Update to generic ADC channel binding on DHSOM systems
ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-testbench
ARM: dts: stm32: adopt generic iio bindings for adc channels on dhcor-drc
ARM: dts: stm32: adopt generic iio bindings for adc channels on emstamp-argon
ARM: dts: stm32: adopt generic iio bindings for adc channels on stm32mp157c-ed1
ARM: dts: stm32: enable adc on stm32mp15xx-dkx boards
ARM: dts: stm32: add vrefint support to adc2 on stm32mp15
...
Link: https://lore.kernel.org/r/080fc303-45c1-6cc0-4c5e-694e730896a6@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
378 lines
8.7 KiB
Plaintext
378 lines
8.7 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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menu "Platform selection"
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config ARCH_ACTIONS
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bool "Actions Semi Platforms"
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select OWL_TIMER
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select PINCTRL
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help
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This enables support for the Actions Semiconductor S900 SoC family.
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config ARCH_SUNXI
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bool "Allwinner sunxi 64-bit SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select RESET_CONTROLLER
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select SUN4I_TIMER
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select SUN6I_R_INTC
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select SUNXI_NMI_INTC
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help
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This enables support for Allwinner sunxi based SoCs like the A64.
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config ARCH_ALPINE
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bool "Annapurna Labs Alpine platform"
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select ALPINE_MSI if PCI
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help
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This enables support for the Annapurna Labs Alpine
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Soc family.
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config ARCH_APPLE
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bool "Apple Silicon SoC family"
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select APPLE_AIC
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help
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This enables support for Apple's in-house ARM SoC family, starting
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with the Apple M1.
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menuconfig ARCH_BCM
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bool "Broadcom SoC Support"
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if ARCH_BCM
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config ARCH_BCM2835
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bool "Broadcom BCM2835 family"
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select TIMER_OF
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select GPIOLIB
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select MFD_CORE
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select PINCTRL
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select PINCTRL_BCM2835
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select ARM_AMBA
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select ARM_GIC
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select ARM_TIMER_SP804
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help
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This enables support for the Broadcom BCM2837 and BCM2711 SoC.
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These SoCs are used in the Raspberry Pi 3 and 4 devices.
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config ARCH_BCM_IPROC
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bool "Broadcom iProc SoC Family"
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select COMMON_CLK_IPROC
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Broadcom iProc based SoCs
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config ARCH_BCMBCA
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bool "Broadcom Broadband Carrier Access (BCA) origin SoC"
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select GPIOLIB
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help
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Say Y if you intend to run the kernel on a Broadcom Broadband ARM-based
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BCA chipset.
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This enables support for Broadcom BCA ARM-based broadband chipsets,
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including the DSL, PON and Wireless family of chips.
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config ARCH_BRCMSTB
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bool "Broadcom Set-Top-Box SoCs"
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select ARCH_HAS_RESET_CONTROLLER
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select GENERIC_IRQ_CHIP
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select PINCTRL
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help
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This enables support for Broadcom's ARMv8 Set Top Box SoCs
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endif
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config ARCH_BERLIN
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bool "Marvell Berlin SoC Family"
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select DW_APB_ICTL
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select DW_APB_TIMER_OF
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select GPIOLIB
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select PINCTRL
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help
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This enables support for Marvell Berlin SoC Family
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config ARCH_BITMAIN
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bool "Bitmain SoC Platforms"
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help
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This enables support for the Bitmain SoC Family.
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config ARCH_EXYNOS
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bool "Samsung Exynos SoC family"
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select COMMON_CLK_SAMSUNG
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select CLKSRC_EXYNOS_MCT
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select EXYNOS_PM_DOMAINS if PM_GENERIC_DOMAINS
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select EXYNOS_PMU
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select PINCTRL
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select PINCTRL_EXYNOS
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select PM_GENERIC_DOMAINS if PM
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select SOC_SAMSUNG
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help
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This enables support for ARMv8 based Samsung Exynos SoC family.
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config ARCH_SPARX5
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bool "Microchip Sparx5 SoC family"
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select PINCTRL
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select DW_APB_TIMER_OF
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help
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This enables support for the Microchip Sparx5 ARMv8-based
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SoC family of TSN-capable gigabit switches.
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The SparX-5 Ethernet switch family provides a rich set of
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switching features such as advanced TCAM-based VLAN and QoS
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processing enabling delivery of differentiated services, and
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security through TCAM-based frame processing using versatile
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content aware processor (VCAP).
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config ARCH_K3
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bool "Texas Instruments Inc. K3 multicore SoC architecture"
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select PM_GENERIC_DOMAINS if PM
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select MAILBOX
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select SOC_TI
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select TI_MESSAGE_MANAGER
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select TI_SCI_PROTOCOL
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select TI_SCI_INTR_IRQCHIP
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select TI_SCI_INTA_IRQCHIP
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select TI_K3_SOCINFO
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help
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This enables support for Texas Instruments' K3 multicore SoC
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architecture.
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config ARCH_LG1K
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bool "LG Electronics LG1K SoC Family"
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help
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This enables support for LG Electronics LG1K SoC Family
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config ARCH_HISI
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bool "Hisilicon SoC Family"
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select ARM_TIMER_SP804
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select HISILICON_IRQ_MBIGEN if PCI
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select PINCTRL
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help
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This enables support for Hisilicon ARMv8 SoC family
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config ARCH_KEEMBAY
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bool "Keem Bay SoC"
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help
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This enables support for Intel Movidius SoC code-named Keem Bay.
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config ARCH_MEDIATEK
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bool "MediaTek SoC Family"
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select ARM_GIC
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select PINCTRL
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select MTK_TIMER
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help
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This enables support for MediaTek MT27xx, MT65xx, MT76xx
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& MT81xx ARMv8 SoCs
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config ARCH_MESON
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bool "Amlogic Platforms"
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help
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This enables support for the arm64 based Amlogic SoCs
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such as the s905, S905X/D, S912, A113X/D or S905X/D2
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config ARCH_MVEBU
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bool "Marvell EBU SoC Family"
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select ARMADA_AP806_SYSCON
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select ARMADA_CP110_SYSCON
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select ARMADA_37XX_CLK
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select MVEBU_GICP
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select MVEBU_ICU
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select MVEBU_ODMI
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select MVEBU_PIC
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select MVEBU_SEI
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select OF_GPIO
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select PINCTRL
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select PINCTRL_ARMADA_37XX
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select PINCTRL_ARMADA_AP806
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select PINCTRL_ARMADA_CP110
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select PINCTRL_AC5
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help
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This enables support for Marvell EBU family, including:
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- Armada 3700 SoC Family
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- Armada 7K SoC Family
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- Armada 8K SoC Family
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- 98DX2530 SoC Family
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menuconfig ARCH_NXP
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bool "NXP SoC support"
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if ARCH_NXP
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config ARCH_LAYERSCAPE
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bool "Freescale Layerscape SoC family"
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select EDAC_SUPPORT
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help
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This enables support for the Freescale Layerscape SoC family.
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config ARCH_MXC
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bool "NXP i.MX SoC family"
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select ARM64_ERRATUM_843419
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select ARM64_ERRATUM_845719 if COMPAT
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select IMX_GPCV2
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select IMX_GPCV2_PM_DOMAINS
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select PM
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select PM_GENERIC_DOMAINS
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select SOC_BUS
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select TIMER_IMX_SYS_CTR
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help
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This enables support for the ARMv8 based SoCs in the
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NXP i.MX family.
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config ARCH_S32
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bool "NXP S32 SoC Family"
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help
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This enables support for the NXP S32 family of processors.
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endif
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config ARCH_MA35
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bool "Nuvoton MA35 Architecture"
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select GPIOLIB
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for the ARMv8 based Nuvoton MA35 series SoCs.
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config ARCH_NPCM
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bool "Nuvoton NPCM Architecture"
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select PINCTRL
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select GPIOLIB
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select NPCM7XX_TIMER
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select RESET_CONTROLLER
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select MFD_SYSCON
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help
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General support for NPCM8xx BMC (Arbel).
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Nuvoton NPCM8xx BMC based on the Cortex A35.
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config ARCH_QCOM
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bool "Qualcomm Platforms"
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select GPIOLIB
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select PINCTRL
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help
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This enables support for the ARMv8 based Qualcomm chipsets.
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config ARCH_REALTEK
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bool "Realtek Platforms"
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select RESET_CONTROLLER
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help
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This enables support for the ARMv8 based Realtek chipsets,
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like the RTD1295.
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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help
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This enables support for the ARMv8 based Renesas SoCs.
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config ARCH_ROCKCHIP
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bool "Rockchip Platforms"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select PM
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select ROCKCHIP_TIMER
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help
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This enables support for the ARMv8 based Rockchip chipsets,
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like the RK3368.
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config ARCH_SEATTLE
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bool "AMD Seattle SoC Family"
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help
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This enables support for AMD Seattle SOC Family
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config ARCH_INTEL_SOCFPGA
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bool "Intel's SoCFPGA ARMv8 Families"
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help
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This enables support for Intel's SoCFPGA ARMv8 families:
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Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
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Agilex and eASIC N5X.
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config ARCH_STM32
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bool "STMicroelectronics STM32 SoC Family"
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select GPIOLIB
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select PINCTRL
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select PINCTRL_STM32MP257
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select ARM_SMC_MBOX
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select ARM_SCMI_PROTOCOL
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select COMMON_CLK_SCMI
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help
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This enables support for ARMv8 based STMicroelectronics
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STM32 family, including:
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- STM32MP25:
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- STM32MP251, STM32MP253, STM32MP255 and STM32MP257.
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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select IRQ_FASTEOI_HIERARCHY_HANDLERS
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config ARCH_TEGRA
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bool "NVIDIA Tegra SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select ARM_GIC_PM
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select CLKSRC_MMIO
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select TIMER_OF
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select GPIOLIB
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select PINCTRL
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select PM
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select PM_GENERIC_DOMAINS
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select RESET_CONTROLLER
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help
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This enables support for the NVIDIA Tegra SoC family.
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config ARCH_TESLA_FSD
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bool "Tesla platform"
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depends on ARCH_EXYNOS
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help
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Support for ARMv8 based Tesla platforms.
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config ARCH_SPRD
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bool "Spreadtrum SoC platform"
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help
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Support for Spreadtrum ARM based SoCs
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config ARCH_THUNDER
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bool "Cavium Inc. Thunder SoC Family"
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help
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This enables support for Cavium's Thunder Family of SoCs.
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config ARCH_THUNDER2
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bool "Cavium ThunderX2 Server Processors"
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select GPIOLIB
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help
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This enables support for Cavium's ThunderX2 CN99XX family of
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server processors.
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config ARCH_UNIPHIER
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bool "Socionext UniPhier SoC Family"
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select ARCH_HAS_RESET_CONTROLLER
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select PINCTRL
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select RESET_CONTROLLER
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help
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This enables support for Socionext UniPhier SoC family.
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config ARCH_VEXPRESS
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bool "ARMv8 software model (Versatile Express)"
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select GPIOLIB
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select PM
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select PM_GENERIC_DOMAINS
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help
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This enables support for the ARMv8 software model (Versatile
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Express).
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config ARCH_VISCONTI
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bool "Toshiba Visconti SoC Family"
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select PINCTRL
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select PINCTRL_VISCONTI
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help
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This enables support for Toshiba Visconti SoCs Family.
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config ARCH_XGENE
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bool "AppliedMicro X-Gene SOC Family"
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help
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This enables support for AppliedMicro X-Gene SOC Family
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config ARCH_ZYNQMP
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bool "Xilinx ZynqMP Family"
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help
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This enables support for Xilinx ZynqMP Family
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endmenu # "Platform selection"
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