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The dss parent_clk_name currently points to a clock node which we use to
change the fclk rate. Now that we have CLK_SET_RATE_PARENT properly set,
we can set the rate directly to the fclk node.
However, we still need to calculate the possible clock rates. For this,
we need the rate of the parent of the current parent_clk.
To simplify the code, this patch changes the parent_clk_name to point to
the above mentioned parent, so that we can get the rate directly.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
ada9443ff4