- mm/radix: Update to tlb functions ric argument from Aneesh Kumar K.V - mm/radix: Flush page walk cache when freeing page table from Aneesh Kumar K.V - mm/hash: Use the correct PPP mask when updating HPTE from Aneesh Kumar K.V - mm/hash: Don't add memory coherence if cache inhibited is set from Aneesh Kumar K.V - mm/radix: Update Radix tree size as per ISA 3.0 from Aneesh Kumar K.V - eeh: Fix invalid cached PE primary bus from Gavin Shan - Fix faults caused by radix patching of SLB miss handler from Michael Ellerman - bpf/jit: Disable classic BPF JIT on ppc64le from Naveen N. Rao -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXbmITAAoJEFHr6jzI4aWANXwQAIUzjKcLpyQWEKwOKfMqBT5T EfsWDqJA/J3mYKNcZyiB7qv1NVPPkU9DSBK0OaAKwYdg5YWKDBl6R3mW+j4di0bP SkFACCyE2WbLTCiz5fzd8l974RUh5jKQpIrObp4/8xp40d0vsyAzz4J7d4HVRsrr BnoTS/KmytsaDQls5kYArxhW6U+Shag586Au1hNt3SS/be8lCNEXLfa3ltCr7WLJ k+xM0KM5kpO9/OK40A64TH7xUZKQIgPMUR5Ct43IJhMeHNnQctLmGQQjRWTrajv1 K/TfrYwCl66xzKaH5G3MKJgqJAJm1LTwGs+2aOn91x5hPrbmW+bLqr1Mm0ukjROz oaANO5fgEQjl0JRGCNAhLHvaoqJX6v5/7GbmFRoaigX4UKJ63nK1ABiwAgKDGnyj OchwwJywU5UIX/+9Qpig3CxQNhEV33Nnp8t+dsg8CPd9o/G0mIe0QP1eGdhD09mM X9eMfN08hLj5ERKvlpW0rrq1b/wizOGmUXbmt02HZi7iLNsyQMwShiOvwOaAvH6/ SzEFBJdp11jNoe4GJDt5rH4HlnTnTAYwcLFMTDCCPdJXy7voI/J+MaAmG89S30dQ ph0+4v/8K2N0VDZ7kkgi0GL1gp9ULkgtimrN5Z0R8U7qEapEW6ybvv+0Ewln742f SCRNVMZgzcwe3CcCKzdn =fxml -----END PGP SIGNATURE----- Merge tag 'powerpc-4.7-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: "mm/radix (Aneesh Kumar K.V): - Update to tlb functions ric argument - Flush page walk cache when freeing page table - Update Radix tree size as per ISA 3.0 mm/hash (Aneesh Kumar K.V): - Use the correct PPP mask when updating HPTE - Don't add memory coherence if cache inhibited is set eeh (Gavin Shan): - Fix invalid cached PE primary bus bpf/jit (Naveen N. Rao): - Disable classic BPF JIT on ppc64le .. and fix faults caused by radix patching of SLB miss handler (Michael Ellerman)" * tag 'powerpc-4.7-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/bpf/jit: Disable classic BPF JIT on ppc64le powerpc: Fix faults caused by radix patching of SLB miss handler powerpc/eeh: Fix invalid cached PE primary bus powerpc/mm/radix: Update Radix tree size as per ISA 3.0 powerpc/mm/hash: Don't add memory coherence if cache inhibited is set powerpc/mm/hash: Use the correct PPP mask when updating HPTE powerpc/mm/radix: Flush page walk cache when freeing page table powerpc/mm/radix: Update to tlb functions ric argument
220 lines
5.9 KiB
C
220 lines
5.9 KiB
C
#ifndef _ASM_POWERPC_BOOK3S_64_PGALLOC_H
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#define _ASM_POWERPC_BOOK3S_64_PGALLOC_H
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/slab.h>
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#include <linux/cpumask.h>
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#include <linux/percpu.h>
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struct vmemmap_backing {
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struct vmemmap_backing *list;
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unsigned long phys;
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unsigned long virt_addr;
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};
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extern struct vmemmap_backing *vmemmap_list;
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/*
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* Functions that deal with pagetables that could be at any level of
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* the table need to be passed an "index_size" so they know how to
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* handle allocation. For PTE pages (which are linked to a struct
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* page for now, and drawn from the main get_free_pages() pool), the
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* allocation size will be (2^index_size * sizeof(pointer)) and
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* allocations are drawn from the kmem_cache in PGT_CACHE(index_size).
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*
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* The maximum index size needs to be big enough to allow any
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* pagetable sizes we need, but small enough to fit in the low bits of
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* any page table pointer. In other words all pagetables, even tiny
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* ones, must be aligned to allow at least enough low 0 bits to
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* contain this value. This value is also used as a mask, so it must
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* be one less than a power of two.
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*/
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#define MAX_PGTABLE_INDEX_SIZE 0xf
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extern struct kmem_cache *pgtable_cache[];
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#define PGT_CACHE(shift) ({ \
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BUG_ON(!(shift)); \
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pgtable_cache[(shift) - 1]; \
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})
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#define PGALLOC_GFP GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO
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extern pte_t *pte_fragment_alloc(struct mm_struct *, unsigned long, int);
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extern void pte_fragment_free(unsigned long *, int);
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extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift);
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#ifdef CONFIG_SMP
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extern void __tlb_remove_table(void *_table);
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#endif
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static inline pgd_t *radix__pgd_alloc(struct mm_struct *mm)
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{
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#ifdef CONFIG_PPC_64K_PAGES
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return (pgd_t *)__get_free_page(PGALLOC_GFP);
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#else
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struct page *page;
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page = alloc_pages(PGALLOC_GFP | __GFP_REPEAT, 4);
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if (!page)
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return NULL;
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return (pgd_t *) page_address(page);
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#endif
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}
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static inline void radix__pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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#ifdef CONFIG_PPC_64K_PAGES
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free_page((unsigned long)pgd);
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#else
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free_pages((unsigned long)pgd, 4);
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#endif
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}
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static inline pgd_t *pgd_alloc(struct mm_struct *mm)
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{
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if (radix_enabled())
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return radix__pgd_alloc(mm);
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return kmem_cache_alloc(PGT_CACHE(PGD_INDEX_SIZE), GFP_KERNEL);
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}
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static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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if (radix_enabled())
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return radix__pgd_free(mm, pgd);
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kmem_cache_free(PGT_CACHE(PGD_INDEX_SIZE), pgd);
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}
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static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
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{
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pgd_set(pgd, __pgtable_ptr_val(pud) | PGD_VAL_BITS);
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}
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static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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return kmem_cache_alloc(PGT_CACHE(PUD_INDEX_SIZE), GFP_KERNEL);
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}
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static inline void pud_free(struct mm_struct *mm, pud_t *pud)
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{
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kmem_cache_free(PGT_CACHE(PUD_INDEX_SIZE), pud);
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}
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static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
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{
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pud_set(pud, __pgtable_ptr_val(pmd) | PUD_VAL_BITS);
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}
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static inline void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
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unsigned long address)
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{
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/*
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* By now all the pud entries should be none entries. So go
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* ahead and flush the page walk cache
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*/
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flush_tlb_pgtable(tlb, address);
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pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE);
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}
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static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
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{
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return kmem_cache_alloc(PGT_CACHE(PMD_CACHE_INDEX), GFP_KERNEL);
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}
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static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
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{
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kmem_cache_free(PGT_CACHE(PMD_CACHE_INDEX), pmd);
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}
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static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
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unsigned long address)
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{
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/*
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* By now all the pud entries should be none entries. So go
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* ahead and flush the page walk cache
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*/
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flush_tlb_pgtable(tlb, address);
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return pgtable_free_tlb(tlb, pmd, PMD_CACHE_INDEX);
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}
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static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
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pte_t *pte)
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{
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pmd_set(pmd, __pgtable_ptr_val(pte) | PMD_VAL_BITS);
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}
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static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
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pgtable_t pte_page)
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{
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pmd_set(pmd, __pgtable_ptr_val(pte_page) | PMD_VAL_BITS);
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}
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static inline pgtable_t pmd_pgtable(pmd_t pmd)
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{
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return (pgtable_t)pmd_page_vaddr(pmd);
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}
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#ifdef CONFIG_PPC_4K_PAGES
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static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
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unsigned long address)
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{
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return (pte_t *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
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}
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static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
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unsigned long address)
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{
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struct page *page;
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pte_t *pte;
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pte = pte_alloc_one_kernel(mm, address);
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if (!pte)
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return NULL;
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page = virt_to_page(pte);
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if (!pgtable_page_ctor(page)) {
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__free_page(page);
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return NULL;
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}
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return pte;
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}
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#else /* if CONFIG_PPC_64K_PAGES */
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static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
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unsigned long address)
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{
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return (pte_t *)pte_fragment_alloc(mm, address, 1);
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}
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static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
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unsigned long address)
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{
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return (pgtable_t)pte_fragment_alloc(mm, address, 0);
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}
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#endif
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static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
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{
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pte_fragment_free((unsigned long *)pte, 1);
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}
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static inline void pte_free(struct mm_struct *mm, pgtable_t ptepage)
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{
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pte_fragment_free((unsigned long *)ptepage, 0);
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}
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static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
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unsigned long address)
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{
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/*
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* By now all the pud entries should be none entries. So go
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* ahead and flush the page walk cache
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*/
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flush_tlb_pgtable(tlb, address);
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pgtable_free_tlb(tlb, table, 0);
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}
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#define check_pgt_cache() do { } while (0)
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#endif /* _ASM_POWERPC_BOOK3S_64_PGALLOC_H */
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