Stefan Agner eaeebffa90 drm/panel: simple: Specify bus width and flags for EDT displays
The display has a 18-Bit parallel LCD interface, require DE to be
active high and data driven by the controller on falling pixel
clock edge (display samples on rising edge).

Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-26 10:57:18 +01:00
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