65c9ad77cb
Add a MODULE_DEVICE_TABLE() on all clocks that can be built as modules to allow auto-load at boot. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Miles Chen <miles.chen@mediatek.com> Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks Link: https://lore.kernel.org/r/20230306140543.1813621-50-angelogioacchino.delregno@collabora.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022 Collabora Ltd.
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* Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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*/
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include "reset.h"
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#define GATE_PERI0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &peri0_cg_regs, \
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_shift, &mtk_clk_gate_ops_setclr)
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#define GATE_PERI1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &peri1_cg_regs, \
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_shift, &mtk_clk_gate_ops_setclr)
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static DEFINE_SPINLOCK(mt8173_clk_lock);
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static const struct mtk_gate_regs peri0_cg_regs = {
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.set_ofs = 0x0008,
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.clr_ofs = 0x0010,
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.sta_ofs = 0x0018,
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};
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static const struct mtk_gate_regs peri1_cg_regs = {
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.set_ofs = 0x000c,
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.clr_ofs = 0x0014,
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.sta_ofs = 0x001c,
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};
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static const char * const uart_ck_sel_parents[] = {
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"clk26m",
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"uart_sel",
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};
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static const struct mtk_composite peri_clks[] = {
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MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
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MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
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MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
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MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
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};
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static const struct mtk_gate peri_gates[] = {
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GATE_DUMMY(CLK_DUMMY, "peri_gate_dummy"),
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/* PERI0 */
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GATE_PERI0(CLK_PERI_NFI, "peri_nfi", "axi_sel", 0),
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GATE_PERI0(CLK_PERI_THERM, "peri_therm", "axi_sel", 1),
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GATE_PERI0(CLK_PERI_PWM1, "peri_pwm1", "axi_sel", 2),
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GATE_PERI0(CLK_PERI_PWM2, "peri_pwm2", "axi_sel", 3),
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GATE_PERI0(CLK_PERI_PWM3, "peri_pwm3", "axi_sel", 4),
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GATE_PERI0(CLK_PERI_PWM4, "peri_pwm4", "axi_sel", 5),
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GATE_PERI0(CLK_PERI_PWM5, "peri_pwm5", "axi_sel", 6),
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GATE_PERI0(CLK_PERI_PWM6, "peri_pwm6", "axi_sel", 7),
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GATE_PERI0(CLK_PERI_PWM7, "peri_pwm7", "axi_sel", 8),
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GATE_PERI0(CLK_PERI_PWM, "peri_pwm", "axi_sel", 9),
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GATE_PERI0(CLK_PERI_USB0, "peri_usb0", "usb20_sel", 10),
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GATE_PERI0(CLK_PERI_USB1, "peri_usb1", "usb20_sel", 11),
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GATE_PERI0(CLK_PERI_AP_DMA, "peri_ap_dma", "axi_sel", 12),
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GATE_PERI0(CLK_PERI_MSDC30_0, "peri_msdc30_0", "msdc50_0_sel", 13),
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GATE_PERI0(CLK_PERI_MSDC30_1, "peri_msdc30_1", "msdc30_1_sel", 14),
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GATE_PERI0(CLK_PERI_MSDC30_2, "peri_msdc30_2", "msdc30_2_sel", 15),
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GATE_PERI0(CLK_PERI_MSDC30_3, "peri_msdc30_3", "msdc30_3_sel", 16),
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GATE_PERI0(CLK_PERI_NLI_ARB, "peri_nli_arb", "axi_sel", 17),
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GATE_PERI0(CLK_PERI_IRDA, "peri_irda", "irda_sel", 18),
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GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
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GATE_PERI0(CLK_PERI_UART1, "peri_uart1", "axi_sel", 20),
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GATE_PERI0(CLK_PERI_UART2, "peri_uart2", "axi_sel", 21),
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GATE_PERI0(CLK_PERI_UART3, "peri_uart3", "axi_sel", 22),
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GATE_PERI0(CLK_PERI_I2C0, "peri_i2c0", "axi_sel", 23),
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GATE_PERI0(CLK_PERI_I2C1, "peri_i2c1", "axi_sel", 24),
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GATE_PERI0(CLK_PERI_I2C2, "peri_i2c2", "axi_sel", 25),
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GATE_PERI0(CLK_PERI_I2C3, "peri_i2c3", "axi_sel", 26),
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GATE_PERI0(CLK_PERI_I2C4, "peri_i2c4", "axi_sel", 27),
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GATE_PERI0(CLK_PERI_AUXADC, "peri_auxadc", "clk26m", 28),
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GATE_PERI0(CLK_PERI_SPI0, "peri_spi0", "spi_sel", 29),
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GATE_PERI0(CLK_PERI_I2C5, "peri_i2c5", "axi_sel", 30),
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GATE_PERI0(CLK_PERI_NFIECC, "peri_nfiecc", "axi_sel", 31),
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/* PERI1 */
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GATE_PERI1(CLK_PERI_SPI, "peri_spi", "spi_sel", 0),
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GATE_PERI1(CLK_PERI_IRRX, "peri_irrx", "spi_sel", 1),
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GATE_PERI1(CLK_PERI_I2C6, "peri_i2c6", "axi_sel", 2),
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};
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static u16 pericfg_rst_ofs[] = { 0x0, 0x4 };
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static const struct mtk_clk_rst_desc clk_rst_desc = {
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.version = MTK_RST_SIMPLE,
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.rst_bank_ofs = pericfg_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
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};
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static const struct mtk_clk_desc peri_desc = {
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.clks = peri_gates,
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.num_clks = ARRAY_SIZE(peri_gates),
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.composite_clks = peri_clks,
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.num_composite_clks = ARRAY_SIZE(peri_clks),
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.clk_lock = &mt8173_clk_lock,
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.rst_desc = &clk_rst_desc,
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};
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static const struct of_device_id of_match_clk_mt8173_pericfg[] = {
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{ .compatible = "mediatek,mt8173-pericfg", .data = &peri_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_pericfg);
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static struct platform_driver clk_mt8173_pericfg_drv = {
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.driver = {
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.name = "clk-mt8173-pericfg",
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.of_match_table = of_match_clk_mt8173_pericfg,
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},
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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};
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module_platform_driver(clk_mt8173_pericfg_drv);
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MODULE_DESCRIPTION("MediaTek MT8173 pericfg clocks driver");
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MODULE_LICENSE("GPL");
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