d9932b4691
Add arm64 Hyper-V vPCI support by implementing the arch specific interfaces. Introduce an IRQ domain and chip specific to Hyper-v vPCI that is based on SPIs. The IRQ domain parents itself to the arch GIC IRQ domain for basic vector management. [bhelgaas: squash in fix from Yang Li <yang.lee@linux.alibaba.com>: https://lore.kernel.org/r/20220112003324.62755-1-yang.lee@linux.alibaba.com] Link: https://lore.kernel.org/r/1641411156-31705-3-git-send-email-sunilmut@linux.microsoft.com Signed-off-by: Sunil Muthuswamy <sunilmut@microsoft.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Michael Kelley <mikelley@microsoft.com>
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This file contains definitions from the Hyper-V Hypervisor Top-Level
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* Functional Specification (TLFS):
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* https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/reference/tlfs
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*
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* Copyright (C) 2021, Microsoft, Inc.
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*
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* Author : Michael Kelley <mikelley@microsoft.com>
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*/
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#ifndef _ASM_HYPERV_TLFS_H
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#define _ASM_HYPERV_TLFS_H
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#include <linux/types.h>
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/*
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* All data structures defined in the TLFS that are shared between Hyper-V
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* and a guest VM use Little Endian byte ordering. This matches the default
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* byte ordering of Linux running on ARM64, so no special handling is required.
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*/
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/*
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* These Hyper-V registers provide information equivalent to the CPUID
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* instruction on x86/x64.
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*/
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#define HV_REGISTER_HYPERVISOR_VERSION 0x00000100 /*CPUID 0x40000002 */
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#define HV_REGISTER_FEATURES 0x00000200 /*CPUID 0x40000003 */
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#define HV_REGISTER_ENLIGHTENMENTS 0x00000201 /*CPUID 0x40000004 */
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/*
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* Group C Features. See the asm-generic version of hyperv-tlfs.h
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* for a description of Feature Groups.
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*/
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/* Crash MSRs available */
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#define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE BIT(8)
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/* STIMER direct mode is available */
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#define HV_STIMER_DIRECT_MODE_AVAILABLE BIT(13)
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/*
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* Synthetic register definitions equivalent to MSRs on x86/x64
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*/
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#define HV_REGISTER_CRASH_P0 0x00000210
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#define HV_REGISTER_CRASH_P1 0x00000211
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#define HV_REGISTER_CRASH_P2 0x00000212
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#define HV_REGISTER_CRASH_P3 0x00000213
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#define HV_REGISTER_CRASH_P4 0x00000214
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#define HV_REGISTER_CRASH_CTL 0x00000215
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#define HV_REGISTER_GUEST_OSID 0x00090002
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#define HV_REGISTER_VP_INDEX 0x00090003
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#define HV_REGISTER_TIME_REF_COUNT 0x00090004
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#define HV_REGISTER_REFERENCE_TSC 0x00090017
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#define HV_REGISTER_SINT0 0x000A0000
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#define HV_REGISTER_SCONTROL 0x000A0010
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#define HV_REGISTER_SIEFP 0x000A0012
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#define HV_REGISTER_SIMP 0x000A0013
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#define HV_REGISTER_EOM 0x000A0014
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#define HV_REGISTER_STIMER0_CONFIG 0x000B0000
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#define HV_REGISTER_STIMER0_COUNT 0x000B0001
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union hv_msi_entry {
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u64 as_uint64[2];
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struct {
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u64 address;
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u32 data;
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u32 reserved;
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} __packed;
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};
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#include <asm-generic/hyperv-tlfs.h>
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#endif
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