John Crispin af14a456c5 MIPS: lantiq: adds code for booting GPHY ... The XRX200 family of SoCs has embedded gigabit PHYs. This patch adds code to boot them up. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4522		2012-11-11 18:47:35 +01:00
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clk.c	MIPS: lantiq: implement support for clkdev api	2012-05-21 14:31:51 +01:00
dma.c	MIPS: lantiq: verbose init of dma core	2012-11-11 18:47:26 +01:00
gptu.c	MIPS: lantiq: adds support for gptu timers	2012-08-23 00:18:25 +02:00
Makefile	OF: pinctrl: MIPS: lantiq: implement lantiq/xway pinctrl support	2012-09-13 10:30:49 +02:00
prom.c	MIPS: lantiq: add xway soc ids	2012-05-15 17:49:23 +02:00
reset.c	MIPS: lantiq: adds code for booting GPHY	2012-11-11 18:47:35 +01:00
sysctrl.c	MIPS: lantiq: adds xrx200 ethernet clock definition	2012-11-11 18:47:31 +01:00