Kan Liang af6cf12970 perf/x86: Expose CPUID enumeration bits for arch LBR ...

The LBR capabilities of Architecture LBR are retrieved from the CPUID
enumeration once at boot time. The capabilities have to be saved for
future usage.

Several new fields are added into structure x86_pmu to indicate the
capabilities. The fields will be used in the following patches.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/1593780569-62993-9-git-send-email-kan.liang@linux.intel.com

2020-07-08 11:38:53 +02:00

..

amd

Merge branch 'x86/cpu' into perf/core, to resolve conflict

2020-03-25 15:20:44 +01:00

intel

perf/x86/intel/lbr: Use dynamic data structure for task_ctx

2020-07-08 11:38:52 +02:00

zhaoxin

x86/perf: Add hardware performance events support for Zhaoxin CPU.

2020-04-30 20:14:35 +02:00

core.c

perf/x86: Add constraint to create guest LBR event without hw counter

2020-07-02 15:51:46 +02:00

Kconfig

treewide: replace '---help---' in Kconfig files with 'help'

2020-06-14 01:57:21 +09:00

Makefile

perf/x86/rapl: Fix RAPL config variable bug

2020-06-02 11:52:56 +02:00

msr.c

perf/x86/msr: Add Tremont support

2020-02-11 13:17:50 +01:00

perf_event.h

perf/x86: Expose CPUID enumeration bits for arch LBR

2020-07-08 11:38:53 +02:00

probe.c

perf/x86/rapl: Make perf_probe_msr() more robust and flexible

2020-05-28 07:58:55 +02:00

probe.h

perf/x86: Add MSR probe interface

2019-06-24 19:28:31 +02:00

rapl.c

perf/x86/rapl: Add AMD Fam17h RAPL support

2020-05-28 07:58:56 +02:00