87f06247e0
The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr> Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __DTS_MARVELL_PXA1928_CLOCK_H
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#define __DTS_MARVELL_PXA1928_CLOCK_H
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/*
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* Clock ID values here correspond to the control register offset/4.
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*/
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/* apb peripherals */
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#define PXA1928_CLK_RTC 0x00
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#define PXA1928_CLK_TWSI0 0x01
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#define PXA1928_CLK_TWSI1 0x02
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#define PXA1928_CLK_TWSI2 0x03
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#define PXA1928_CLK_TWSI3 0x04
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#define PXA1928_CLK_OWIRE 0x05
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#define PXA1928_CLK_KPC 0x06
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#define PXA1928_CLK_TB_ROTARY 0x07
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#define PXA1928_CLK_SW_JTAG 0x08
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#define PXA1928_CLK_TIMER1 0x09
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#define PXA1928_CLK_UART0 0x0b
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#define PXA1928_CLK_UART1 0x0c
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#define PXA1928_CLK_UART2 0x0d
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#define PXA1928_CLK_GPIO 0x0e
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#define PXA1928_CLK_PWM0 0x0f
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#define PXA1928_CLK_PWM1 0x10
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#define PXA1928_CLK_PWM2 0x11
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#define PXA1928_CLK_PWM3 0x12
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#define PXA1928_CLK_SSP0 0x13
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#define PXA1928_CLK_SSP1 0x14
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#define PXA1928_CLK_SSP2 0x15
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#define PXA1928_CLK_TWSI4 0x1f
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#define PXA1928_CLK_TWSI5 0x20
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#define PXA1928_CLK_UART3 0x22
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#define PXA1928_CLK_THSENS_GLOB 0x24
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#define PXA1928_CLK_THSENS_CPU 0x26
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#define PXA1928_CLK_THSENS_VPU 0x27
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#define PXA1928_CLK_THSENS_GC 0x28
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/* axi peripherals */
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#define PXA1928_CLK_SDH0 0x15
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#define PXA1928_CLK_SDH1 0x16
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#define PXA1928_CLK_USB 0x17
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#define PXA1928_CLK_NAND 0x18
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#define PXA1928_CLK_DMA 0x19
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#define PXA1928_CLK_SDH2 0x3a
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#define PXA1928_CLK_SDH3 0x3b
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#define PXA1928_CLK_HSIC 0x3e
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#define PXA1928_CLK_SDH4 0x57
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#define PXA1928_CLK_GC3D 0x5d
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#define PXA1928_CLK_GC2D 0x5f
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#endif
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