Jisheng Zhang b0fd4b1bf9 riscv: mm: fix wrong phys_ram_base value for RV64 ... Currently, if 64BIT and !XIP_KERNEL, the phys_ram_base is always 0, no matter the real start of dram reported by memblock is. Fixes: 6d7f91d914 ("riscv: Get rid of CONFIG_PHYS_RAM_BASE in kernel physical address conversion") Signed-off-by: Jisheng Zhang <jszhang@kernel.org> Reviewed-by: Alexandre Ghiti <alex@ghiti.fr> Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-01-09 13:51:48 -08:00
..
boot	riscv: dts: sifive: fu540-c000: Fix PLIC node	2022-01-09 10:11:44 -08:00
configs	RISC-V: defconfigs: Remove redundant K210 DT source	2022-01-06 09:41:03 -08:00
errata	riscv: errata: alternative: mark vendor_patch_func __initdata	2022-01-09 11:02:46 -08:00
include	RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n	2022-01-09 12:13:31 -08:00
kernel	RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n	2022-01-09 12:13:31 -08:00
kvm	RISC-V: KVM: fix boolreturn.cocci warnings	2021-11-01 17:35:17 +05:30
lib	riscv: extable: consolidate definitions	2022-01-05 17:52:47 -08:00
mm	riscv: mm: fix wrong phys_ram_base value for RV64	2022-01-09 13:51:48 -08:00
net	riscv: extable: add type and data fields	2022-01-05 17:52:54 -08:00
Kbuild	kbuild: use more subdir- for visiting subdirectories while cleaning	2021-10-24 13:49:46 +09:00
Kconfig	riscv/mm: Enable THP migration	2022-01-07 15:54:28 -08:00
Kconfig.debug	RISC-V: Remove EARLY_PRINTK support	2018-12-17 10:23:46 -08:00
Kconfig.erratas	riscv: enable SiFive errata CIP-453 and CIP-1200 Kconfig only if CONFIG_64BIT=y	2021-05-06 09:40:13 -07:00
Kconfig.socs	riscv: sifive: fix Kconfig errata warning	2021-06-12 17:20:50 -07:00
Makefile	RISC-V Patches for the 5.16 Merge Window, Part 1	2021-11-13 09:15:42 -08:00