b132c2a8ea
MT8195 VPPSYS0/1 will be probed by the compatible name in the mtk-mmsys driver and then probe its own clock driver as a platform driver. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> Link: https://lore.kernel.org/r/20230118031509.29834-4-moudy.ho@mediatek.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
140 lines
5.4 KiB
C
140 lines
5.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2021 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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static const struct mtk_gate_regs vpp0_0_cg_regs = {
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.set_ofs = 0x24,
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.clr_ofs = 0x28,
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.sta_ofs = 0x20,
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};
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static const struct mtk_gate_regs vpp0_1_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x34,
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.sta_ofs = 0x2c,
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};
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static const struct mtk_gate_regs vpp0_2_cg_regs = {
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.set_ofs = 0x3c,
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.clr_ofs = 0x40,
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.sta_ofs = 0x38,
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};
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#define GATE_VPP0_0(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VPP0_1(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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#define GATE_VPP0_2(_id, _name, _parent, _shift) \
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GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
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static const struct mtk_gate vpp0_clks[] = {
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/* VPP0_0 */
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GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
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GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
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GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp", 7),
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GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp", 8),
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GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx", "top_vpp", 10),
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GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx", "top_vpp", 11),
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GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
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GATE_VPP0_0(CLK_VPP0_VPP02VPP1_RELAY, "vpp0_vpp02vpp1_relay", "top_vpp", 14),
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GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC, "vpp0_vpp12vpp0_async", "top_vpp", 15),
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GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top", "top_vpp", 16),
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GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp", 17),
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GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp", 18),
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/* VPP0_1 */
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GATE_VPP0_1(CLK_VPP0_SMI_COMMON, "vpp0_smi_common", "top_vpp", 0),
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GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0, "vpp0_gals_vdo0_larb0", "top_vpp", 1),
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GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1, "vpp0_gals_vdo0_larb1", "top_vpp", 2),
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GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS, "vpp0_gals_vencsys", "top_vpp", 3),
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GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1, "vpp0_gals_vencsys_core1", "top_vpp", 4),
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GATE_VPP0_1(CLK_VPP0_GALS_INFRA, "vpp0_gals_infra", "top_vpp", 5),
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GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS, "vpp0_gals_camsys", "top_vpp", 6),
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GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5, "vpp0_gals_vpp1_larb5", "top_vpp", 7),
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GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6, "vpp0_gals_vpp1_larb6", "top_vpp", 8),
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GATE_VPP0_1(CLK_VPP0_SMI_REORDER, "vpp0_smi_reorder", "top_vpp", 9),
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GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu", "top_vpp", 10),
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GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS, "vpp0_gals_imgsys_camsys", "top_vpp", 11),
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GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp", 12),
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GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp", 13),
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GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1", "top_vpp", 16),
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GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER, "vpp0_smi_sub_common_reorder", "top_vpp", 17),
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GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp", 18),
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GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4, "vpp0_smi_common_larb4", "top_vpp", 19),
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GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1, "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
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GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPE, "vpp0_gals_vpp1_wpe", "top_vpp", 21),
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GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1, "vpp0_gals_vdo0_vdo1_vencsys_core1",
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"top_vpp", 22),
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GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp", 23),
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GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp", 24),
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GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp", "top_vpp", 25),
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GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color", "top_vpp", 26),
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GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp", 27),
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/* VPP0_2 */
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GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay", "top_wpe_vpp", 0),
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GATE_VPP0_2(CLK_VPP0_WARP0_MDP_DL_ASYNC, "vpp0_warp0_mdp_dl_async", "top_wpe_vpp", 1),
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GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay", "top_wpe_vpp", 2),
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GATE_VPP0_2(CLK_VPP0_WARP1_MDP_DL_ASYNC, "vpp0_warp1_mdp_dl_async", "top_wpe_vpp", 3),
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};
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static int clk_mt8195_vpp0_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->parent->of_node;
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struct clk_hw_onecell_data *clk_data;
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int r;
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clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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r = mtk_clk_register_gates(dev, node, vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
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if (r)
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goto free_vpp0_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_gates;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_gates:
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mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
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free_vpp0_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static int clk_mt8195_vpp0_remove(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->parent->of_node;
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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of_clk_del_provider(node);
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mtk_clk_unregister_gates(vpp0_clks, ARRAY_SIZE(vpp0_clks), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt8195_vpp0_drv = {
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.probe = clk_mt8195_vpp0_probe,
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.remove = clk_mt8195_vpp0_remove,
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.driver = {
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.name = "clk-mt8195-vpp0",
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},
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};
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builtin_platform_driver(clk_mt8195_vpp0_drv);
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