609cc5e1a8
As part of the effort to improve the MediaTek clk drivers, the next step
is to switch from the old 'struct clk' clk prodivder APIs to the new
'struct clk_hw' ones.
Instead of adding new APIs to the MediaTek clk driver library mirroring
the existing ones, moving all drivers to the new APIs, and then removing
the old ones, just migrate everything at the same time. This involves
replacing 'struct clk' with 'struct clk_hw', and 'struct clk_onecell_data'
with 'struct clk_hw_onecell_data', and fixing up all usages.
For now, the clk_register() and co. usage is retained, with __clk_get_hw()
and (struct clk_hw *)->clk used to bridge the difference between the APIs.
These will be replaced in subsequent patches.
Fix up mtk_{alloc,free}_clk_data to use 'struct clk_hw' by hand. Fix up
all other affected call sites with the following coccinelle script.
// Replace type
@@
@@
- struct clk_onecell_data
+ struct clk_hw_onecell_data
// Replace of_clk_add_provider() & of_clk_src_simple_get()
@@
expression NP, DATA;
symbol of_clk_src_onecell_get;
@@
- of_clk_add_provider(
+ of_clk_add_hw_provider(
NP,
- of_clk_src_onecell_get,
+ of_clk_hw_onecell_get,
DATA
)
// Fix register/unregister
@@
identifier CD;
expression E;
identifier fn =~ "unregister";
@@
fn(...,
- CD->clks[E]
+ CD->hws[E]->clk
,...
);
// Fix calls to clk_prepare_enable()
@@
identifier CD;
expression E;
@@
clk_prepare_enable(
- CD->clks[E]
+ CD->hws[E]->clk
);
// Fix pointer assignment
@@
identifier CD;
identifier CLK;
expression E;
@@
- CD->clks[E]
+ CD->hws[E]
=
(
- CLK
+ __clk_get_hw(CLK)
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ERR_PTR(...)
)
;
// Fix pointer usage
@@
identifier CD;
expression E;
@@
- CD->clks[E]
+ CD->hws[E]
// Fix mtk_clk_pll_get_base()
@@
symbol clk, hw, data;
@@
mtk_clk_pll_get_base(
- struct clk *clk,
+ struct clk_hw *hw,
const struct mtk_pll_data *data
) {
- struct clk_hw *hw = __clk_get_hw(clk);
...
}
// Fix mtk_clk_pll_get_base() usage
@@
identifier CD;
expression E;
@@
mtk_clk_pll_get_base(
- CD->clks[E]
+ CD->hws[E]->clk
,...
);
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Link: https://lore.kernel.org/r/20220519071610.423372-4-wenst@chromium.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
109 lines
2.6 KiB
C
109 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright (c) 2022 MediaTek Inc.
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// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/mt8186-clk.h>
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#include "clk-mtk.h"
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static const char * const mcu_armpll_ll_parents[] = {
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"clk26m",
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"armpll_ll",
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"mainpll",
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"univpll_d2"
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};
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static const char * const mcu_armpll_bl_parents[] = {
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"clk26m",
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"armpll_bl",
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"mainpll",
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"univpll_d2"
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};
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static const char * const mcu_armpll_bus_parents[] = {
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"clk26m",
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"ccipll",
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"mainpll",
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"univpll_d2"
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};
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/*
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* We only configure the CPU muxes when adjust CPU frequency in MediaTek CPUFreq Driver.
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* Other fields like divider always keep the same value. (set once in bootloader)
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*/
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static struct mtk_composite mcu_muxes[] = {
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/* CPU_PLLDIV_CFG0 */
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MUX(CLK_MCU_ARMPLL_LL_SEL, "mcu_armpll_ll_sel", mcu_armpll_ll_parents, 0x2A0, 9, 2),
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/* CPU_PLLDIV_CFG1 */
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MUX(CLK_MCU_ARMPLL_BL_SEL, "mcu_armpll_bl_sel", mcu_armpll_bl_parents, 0x2A4, 9, 2),
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/* BUS_PLLDIV_CFG */
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MUX(CLK_MCU_ARMPLL_BUS_SEL, "mcu_armpll_bus_sel", mcu_armpll_bus_parents, 0x2E0, 9, 2),
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};
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static const struct of_device_id of_match_clk_mt8186_mcu[] = {
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{ .compatible = "mediatek,mt8186-mcusys", },
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{}
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};
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static int clk_mt8186_mcu_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
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void __iomem *base;
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clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
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if (!clk_data)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base)) {
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r = PTR_ERR(base);
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goto free_mcu_data;
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}
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r = mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
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NULL, clk_data);
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if (r)
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goto free_mcu_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_composite_muxes;
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platform_set_drvdata(pdev, clk_data);
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return r;
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unregister_composite_muxes:
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mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
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free_mcu_data:
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mtk_free_clk_data(clk_data);
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return r;
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}
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static int clk_mt8186_mcu_remove(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
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struct device_node *node = pdev->dev.of_node;
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of_clk_del_provider(node);
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mtk_clk_unregister_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), clk_data);
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mtk_free_clk_data(clk_data);
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return 0;
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}
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static struct platform_driver clk_mt8186_mcu_drv = {
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.probe = clk_mt8186_mcu_probe,
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.remove = clk_mt8186_mcu_remove,
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.driver = {
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.name = "clk-mt8186-mcu",
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.of_match_table = of_match_clk_mt8186_mcu,
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},
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};
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builtin_platform_driver(clk_mt8186_mcu_drv);
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