25a068b8e9
Jan Kiszka reported that the x2apic_wrmsr_fence() function uses a plain MFENCE while the Intel SDM (10.12.3 MSR Access in x2APIC Mode) calls for MFENCE; LFENCE. Short summary: we have special MSRs that have weaker ordering than all the rest. Add fencing consistent with current SDM recommendations. This is not known to cause any issues in practice, only in theory. Longer story below: The reason the kernel uses a different semantic is that the SDM changed (roughly in late 2017). The SDM changed because folks at Intel were auditing all of the recommended fences in the SDM and realized that the x2apic fences were insufficient. Why was the pain MFENCE judged insufficient? WRMSR itself is normally a serializing instruction. No fences are needed because the instruction itself serializes everything. But, there are explicit exceptions for this serializing behavior written into the WRMSR instruction documentation for two classes of MSRs: IA32_TSC_DEADLINE and the X2APIC MSRs. Back to x2apic: WRMSR is *not* serializing in this specific case. But why is MFENCE insufficient? MFENCE makes writes visible, but only affects load/store instructions. WRMSR is unfortunately not a load/store instruction and is unaffected by MFENCE. This means that a non-serializing WRMSR could be reordered by the CPU to execute before the writes made visible by the MFENCE have even occurred in the first place. This means that an x2apic IPI could theoretically be triggered before there is any (visible) data to process. Does this affect anything in practice? I honestly don't know. It seems quite possible that by the time an interrupt gets to consume the (not yet) MFENCE'd data, it has become visible, mostly by accident. To be safe, add the SDM-recommended fences for all x2apic WRMSRs. This also leaves open the question of the _other_ weakly-ordered WRMSR: MSR_IA32_TSC_DEADLINE. While it has the same ordering architecture as the x2APIC MSRs, it seems substantially less likely to be a problem in practice. While writes to the in-memory Local Vector Table (LVT) might theoretically be reordered with respect to a weakly-ordered WRMSR like TSC_DEADLINE, the SDM has this to say: In x2APIC mode, the WRMSR instruction is used to write to the LVT entry. The processor ensures the ordering of this write and any subsequent WRMSR to the deadline; no fencing is required. But, that might still leave xAPIC exposed. The safest thing to do for now is to add the extra, recommended LFENCE. [ bp: Massage commit message, fix typos, drop accidentally added newline to tools/arch/x86/include/asm/barrier.h. ] Reported-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> Cc: <stable@vger.kernel.org> Link: https://lkml.kernel.org/r/20200305174708.F77040DD@viggo.jf.intel.com
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_BARRIER_H
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#define _ASM_X86_BARRIER_H
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#include <asm/alternative.h>
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#include <asm/nops.h>
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/*
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* Force strict CPU ordering.
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* And yes, this might be required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_X86_32
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#define mb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "mfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#define rmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "lfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#define wmb() asm volatile(ALTERNATIVE("lock; addl $0,-4(%%esp)", "sfence", \
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X86_FEATURE_XMM2) ::: "memory", "cc")
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#else
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#define mb() asm volatile("mfence":::"memory")
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#define rmb() asm volatile("lfence":::"memory")
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#define wmb() asm volatile("sfence" ::: "memory")
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#endif
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/**
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* array_index_mask_nospec() - generate a mask that is ~0UL when the
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* bounds check succeeds and 0 otherwise
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* @index: array element index
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* @size: number of elements in array
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*
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* Returns:
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* 0 - (index < size)
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*/
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static inline unsigned long array_index_mask_nospec(unsigned long index,
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unsigned long size)
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{
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unsigned long mask;
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asm volatile ("cmp %1,%2; sbb %0,%0;"
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:"=r" (mask)
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:"g"(size),"r" (index)
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:"cc");
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return mask;
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}
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/* Override the default implementation from linux/nospec.h. */
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#define array_index_mask_nospec array_index_mask_nospec
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/* Prevent speculative execution past this barrier. */
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#define barrier_nospec() alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC)
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#define dma_rmb() barrier()
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#define dma_wmb() barrier()
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#ifdef CONFIG_X86_32
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#define __smp_mb() asm volatile("lock; addl $0,-4(%%esp)" ::: "memory", "cc")
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#else
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#define __smp_mb() asm volatile("lock; addl $0,-4(%%rsp)" ::: "memory", "cc")
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#endif
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#define __smp_rmb() dma_rmb()
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#define __smp_wmb() barrier()
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#define __smp_store_mb(var, value) do { (void)xchg(&var, value); } while (0)
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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/* Atomic operations are already serializing on x86 */
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#define __smp_mb__before_atomic() do { } while (0)
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#define __smp_mb__after_atomic() do { } while (0)
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#include <asm-generic/barrier.h>
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/*
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* Make previous memory operations globally visible before
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* a WRMSR.
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*
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* MFENCE makes writes visible, but only affects load/store
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* instructions. WRMSR is unfortunately not a load/store
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* instruction and is unaffected by MFENCE. The LFENCE ensures
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* that the WRMSR is not reordered.
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*
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* Most WRMSRs are full serializing instructions themselves and
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* do not require this barrier. This is only required for the
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* IA32_TSC_DEADLINE and X2APIC MSRs.
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*/
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static inline void weak_wrmsr_fence(void)
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{
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asm volatile("mfence; lfence" : : : "memory");
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}
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#endif /* _ASM_X86_BARRIER_H */
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