a08082f8e4
Add a selftest to check if endianness is flipped inadvertently to BE (MSR.LE set to zero) on BE and LE machines when a trap is caught in transactional mode and load_fp and load_vec are zero, i.e. when MSR.FP and MSR.VEC are zeroed (disabled). Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
17 lines
247 B
Plaintext
17 lines
247 B
Plaintext
tm-resched-dscr
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tm-syscall
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tm-signal-msr-resv
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tm-signal-stack
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tm-vmxcopy
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tm-fork
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tm-tar
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tm-tmspr
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tm-exec
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tm-signal-context-chk-fpu
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tm-signal-context-chk-gpr
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tm-signal-context-chk-vmx
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tm-signal-context-chk-vsx
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tm-vmx-unavail
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tm-unavailable
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tm-trap
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