7e842d70fe
HyperFlash devices fail to probe:
rpc-if-hyperflash rpc-if-hyperflash: probing of hyperbus device failed
In HyperFlash or Octal-SPI Flash mode, the Transfer Data Enable bits
(SPIDE) in the Manual Mode Enable Setting Register (SMENR) are derived
from half of the transfer size, cfr. the rpcif_bits_set() helper
function. However, rpcif_reg_{read,write}() does not take the bus size
into account, and does not double all Manual Mode Data Register access
sizes when communicating with a HyperFlash or Octal-SPI Flash device.
Fix this, and avoid the back-and-forth conversion between transfer size
and Transfer Data Enable bits, by explicitly storing the transfer size
in struct rpcif, and using that value to determine access size in
rpcif_reg_{read,write}().
Enforce that the "high" Manual Mode Read/Write Data Registers
(SM[RW]DR1) are only used for 8-byte data accesses.
While at it, forbid writing to the Manual Mode Read Data Registers,
as they are read-only.
Fixes: fff53a551d ("memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/cde9bfacf704c81865f57b15d1b48a4793da4286.1649681476.git.geert+renesas@glider.be
Link: https://lore.kernel.org/r/20220420070526.9367-1-krzysztof.kozlowski@linaro.org'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
105 lines
1.9 KiB
C
105 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Renesas RPC-IF core driver
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*
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* Copyright (C) 2018~2019 Renesas Solutions Corp.
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* Copyright (C) 2019 Macronix International Co., Ltd.
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* Copyright (C) 2019-2020 Cogent Embedded, Inc.
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*/
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#ifndef __RENESAS_RPC_IF_H
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#define __RENESAS_RPC_IF_H
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#include <linux/pm_runtime.h>
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#include <linux/types.h>
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enum rpcif_data_dir {
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RPCIF_NO_DATA,
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RPCIF_DATA_IN,
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RPCIF_DATA_OUT,
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};
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struct rpcif_op {
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struct {
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u8 buswidth;
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u8 opcode;
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bool ddr;
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} cmd, ocmd;
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struct {
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u8 nbytes;
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u8 buswidth;
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bool ddr;
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u64 val;
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} addr;
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struct {
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u8 ncycles;
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u8 buswidth;
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} dummy;
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struct {
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u8 nbytes;
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u8 buswidth;
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bool ddr;
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u32 val;
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} option;
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struct {
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u8 buswidth;
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unsigned int nbytes;
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enum rpcif_data_dir dir;
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bool ddr;
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union {
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void *in;
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const void *out;
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} buf;
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} data;
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};
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enum rpcif_type {
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RPCIF_RCAR_GEN3,
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RPCIF_RZ_G2L,
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};
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struct rpcif {
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struct device *dev;
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void __iomem *base;
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void __iomem *dirmap;
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struct regmap *regmap;
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struct reset_control *rstc;
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size_t size;
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enum rpcif_type type;
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enum rpcif_data_dir dir;
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u8 bus_size;
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u8 xfer_size;
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void *buffer;
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u32 xferlen;
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u32 smcr;
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u32 smadr;
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u32 command; /* DRCMR or SMCMR */
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u32 option; /* DROPR or SMOPR */
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u32 enable; /* DRENR or SMENR */
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u32 dummy; /* DRDMCR or SMDMCR */
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u32 ddr; /* DRDRENR or SMDRENR */
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};
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int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
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int rpcif_hw_init(struct rpcif *rpc, bool hyperflash);
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void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
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size_t *len);
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int rpcif_manual_xfer(struct rpcif *rpc);
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ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf);
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static inline void rpcif_enable_rpm(struct rpcif *rpc)
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{
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pm_runtime_enable(rpc->dev);
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}
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static inline void rpcif_disable_rpm(struct rpcif *rpc)
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{
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pm_runtime_disable(rpc->dev);
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}
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#endif // __RENESAS_RPC_IF_H
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